A8.6.30

llvm-svn: 96523

* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.

llvm-svn: 96521

B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.

llvm-svn: 96519

llvm-svn: 96490

A8.6.18  BFI - Bitfield insert (Encoding A1)

llvm-svn: 96462

indentation.  No functional changes.

llvm-svn: 96418

build failures due to my fix for pr6111.

llvm-svn: 96402

llvm-svn: 96401

llvm-svn: 96393

llvm-svn: 96388

to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.

llvm-svn: 96384

llvm-svn: 96383

They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.

llvm-svn: 96381

o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)

llvm-svn: 96380

branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.

llvm-svn: 96360

We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.

llvm-svn: 96297

llvm-svn: 96288

IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255

change to SelectionDAG build APIs.

llvm-svn: 96230

as suggested by Bob Wilson.

llvm-svn: 96153

llvm-svn: 96075

created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.

llvm-svn: 96069

llvm-svn: 96063

Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032

Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.

llvm-svn: 96023

llvm-svn: 96019

llvm-svn: 96010

llvm-svn: 95999

MRRC, MRRc2.  For disassembly only.

llvm-svn: 95955

llvm-svn: 95916

Sorry!

llvm-svn: 95892

A8.6.297

llvm-svn: 95885

llvm-svn: 95884

as the "Permanently UNDEFINED" instruction.

llvm-svn: 95873

llvm-svn: 95784

OutStreamer.AddBlankLine instead of textually.

llvm-svn: 95734

A8.6.279

llvm-svn: 95713

A8.6.335 & A8.6.336

llvm-svn: 95703

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686