Commits · 1dc45d8df4194cebf3dd6843e429499c27579773 · Roger Ferrer / llvm-epi-0.8

Dec 22, 2011
- Move the Mips only bits of the ELF writer to lib/Target/Mips. · 1dc45d8d
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147133
```
  1dc45d8d
- Make the virtual methods in ARMELFObjectWriter public. · 84d00f11
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147132
```
  84d00f11
- Move the MBlaze ELF writer bits to lib/Target/MBlaze. · cc369ac0
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147129
```
  cc369ac0
- Fix cmake. · 428b9ee0
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147126
```
  428b9ee0
- Move PPC bits to lib/Target/PowerPC. · 38a400df
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147124
```
  38a400df
- Hopefully fix the cmake build. · 2da9777c
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147121
```
  2da9777c
- Fix name in comments. · 4449b212
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147119
```
  4449b212
- Local dynamic TLS model for direct object output. Create the correct TLS MIPS · e2eed964
  Akira Hatanaka authored Dec 22, 2011
```
ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118
```
  e2eed964
- Unbreak cmake build after r147115. · 32a756b7
  Richard Smith authored Dec 22, 2011
```
llvm-svn: 147117
```
  32a756b7
- Move the ARM specific parts of the ELF writer to Target/ARM. · a0124055
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147115
```
  a0124055
- ARM NEON mnemonic aliase for vrecpeq. · 2b80dad5
  Jim Grosbach authored Dec 21, 2011
```
llvm-svn: 147109
```
  2b80dad5
- ARM VFP optional data type on VMOV GPR<-->SPR. · 7869d8c0
  Jim Grosbach authored Dec 21, 2011
```
llvm-svn: 147104
```
  7869d8c0
- ARM NEON optional data type on VSWP instructions. · 260b4b33
  Jim Grosbach authored Dec 21, 2011
```
llvm-svn: 147103
```
  260b4b33
- ARM NEON mnemonic aliases for vzipq and vswpq. · a50e24fc
  Jim Grosbach authored Dec 21, 2011
```
llvm-svn: 147102
```
  a50e24fc
Dec 21, 2011
- ARM asm parser should be more lenient w/ .thumb_func directive. · 1152cc0c
  Jim Grosbach authored Dec 21, 2011
```
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

llvm-svn: 147100
```
  1152cc0c
- Thumb2 assembly parsing of 'mov rd, rn, rrx'. · 8c59bbc1
  Jim Grosbach authored Dec 21, 2011
```
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096
```
  8c59bbc1
- Fix 80-column violations. · 3172488c
  Chad Rosier authored Dec 21, 2011
```
llvm-svn: 147095
```
  3172488c
- Thumb2 assembly parsing of 'mov(register shifted register)' aliases. · b3ef713e
  Jim Grosbach authored Dec 21, 2011
```
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094
```
  b3ef713e
- Move common code into an MRI function. · 3588a43e
  Jakob Stoklund Olesen authored Dec 21, 2011
```
llvm-svn: 147071
```
  3588a43e
- ARM NEON assmebly parsing for VLD2 to all lanes instructions. · c80a2643
  Jim Grosbach authored Dec 21, 2011
```
llvm-svn: 147069
```
  c80a2643
- No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't · 3ede4141
  Chad Rosier authored Dec 21, 2011
```
necessary.  Please chime in if I'm mistaken.

llvm-svn: 147065
```
  3ede4141
- Fix a couple of copy-n-paste bugs. Noticed by George Russell! · 7248bda5
  Chad Rosier authored Dec 21, 2011
```
llvm-svn: 147064
```
  7248bda5
- Move the X86 specific bits of the ELF writer to the Target/X86 directory. · b264d338
  Rafael Espindola authored Dec 21, 2011
```
Other targets will follow shortly.

llvm-svn: 147060
```
  b264d338
- Reduce the exposure of Triple::OSType in the ELF object writer. This will · 1ad4095d
  Rafael Espindola authored Dec 21, 2011
```
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059
```
  1ad4095d
- Remove mode specific disassembler classes and just call X86GenericDisassembler... · b8b1b4c1
  Craig Topper authored Dec 21, 2011
```
Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.

llvm-svn: 147046
```
  b8b1b4c1
- Fix typo in a couple comments · f3018841
  Craig Topper authored Dec 21, 2011
```
llvm-svn: 147045
```
  f3018841
- Fix a couple of copy-n-paste bugs. Noticed by George Russell. · dc8a1aae
  Evan Cheng authored Dec 21, 2011
```
llvm-svn: 147032
```
  dc8a1aae
- ARM assembly parsing allows constant expressions for lane indices. · 7de7ab83
  Jim Grosbach authored Dec 21, 2011
```
llvm-svn: 147028
```
  7de7ab83
- ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. · c5af54ec
  Jim Grosbach authored Dec 21, 2011
```
llvm-svn: 147025
```
  c5af54ec
- Fix bug in zero-store peephole pattern reported in pr11615. · 964c891e
  Akira Hatanaka authored Dec 21, 2011
```
The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024
```
  964c891e
- Expand 64-bit CTLZ nodes if target architecture does not support it. Add test · 1d8efaba
  Akira Hatanaka authored Dec 21, 2011
```
case for DCLO and DCLZ.

llvm-svn: 147022
```
  1d8efaba
- Expand 64-bit CTPOP and CTTZ. · 410ce9cb
  Akira Hatanaka authored Dec 21, 2011
```
llvm-svn: 147021
```
  410ce9cb
- Expand 64-bit atomic load and store. · 91c052c4
  Akira Hatanaka authored Dec 21, 2011
```
llvm-svn: 147019
```
  91c052c4
- Add definition of DSBH (Double Swap Bytes within Halfwords) and · 4706ac97
  Akira Hatanaka authored Dec 20, 2011
```
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
```
  4706ac97
- Add definition of WSBH (Word Swap Bytes within Halfwords), which is an · 43c1ff4d
  Akira Hatanaka authored Dec 20, 2011
```
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015
```
  43c1ff4d
- 64-bit uint-fp conversion nodes are expanded. · 79aed157
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147014
```
  79aed157
- Enable custom lowering DYNAMIC_STACKALLOC nodes. · 2bb8d068
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147013
```
  2bb8d068
- Set the correct stack pointer register that should be saved or restored. · 8e2c02e2
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147012
```
  8e2c02e2
- ARM .req register name aliases are case insensitive, just like regnames. · cd22e4a8
  Jim Grosbach authored Dec 20, 2011
```
llvm-svn: 147009
```
  cd22e4a8
- Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates · cb2a85bc
  Akira Hatanaka authored Dec 20, 2011
```
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008
```
  cb2a85bc