If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.

This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll

llvm-svn: 36536

    CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll

llvm-svn: 36534

llvm-svn: 36524

CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326

llvm-svn: 36510

llvm-svn: 36501

llvm-svn: 36499

successfully! woohoo...

llvm-svn: 36496

llvm-svn: 36490

llvm-svn: 36485

llvm-svn: 36483

llvm-svn: 36473

llvm-svn: 36458

llvm-svn: 36452

Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction.

llvm-svn: 36451

llvm-svn: 36449

llvm-svn: 36447

llvm-svn: 36445

will follow.

llvm-svn: 36435

- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.

llvm-svn: 36434

llvm-svn: 36431

llvm-svn: 36425

llvm-svn: 36422

llvm-svn: 36420

This fixes CodeGen/X86/2007-04-24-VectorCrash.ll

llvm-svn: 36413

real vector type in this case.

llvm-svn: 36402

tests always being true in the process.

llvm-svn: 36387

llvm-svn: 36383

llvm-svn: 36368

llvm-svn: 36356

llvm-svn: 36318

llvm-svn: 36309

add support for alignment attributes on load/store instructions

llvm-svn: 36301

llvm-svn: 36290

X86 32 bits.

llvm-svn: 36283

llvm-svn: 36250

llvm-svn: 36245

single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244

llvm-svn: 36242

llvm-svn: 36240

llvm-svn: 36233