a pretification of the IR.

llvm-svn: 60973

width register load followed by a truncating
store for the copy, since the load will not place
the value in the lower bits.  Probably partial
loads/stores can never happen here, but fix it
anyway.

llvm-svn: 60972

llvm-svn: 60971

llvm-svn: 60965

use of illegal integer types: instead, use a stack slot
and copying via integer registers.  The existing code
is still used if the bitconvert is to a legal integer
type.

This fires on the PPC testcases 2007-09-08-unaligned.ll
and vec_misaligned.ll.  It looks like equivalent code
is generated with these changes, just permuted, but
it's hard to tell.

With these changes, nothing in LegalizeDAG produces
illegal integer types anymore.  This is a prerequisite
for removing the LegalizeDAG type legalization code.

While there I noticed that the existing code doesn't
handle trunc store of f64 to f32: it turns this into
an i64 store, which represents a 4 byte stack smash.
I added a FIXME about this.  Hopefully someone more
motivated than I am will take care of it.

llvm-svn: 60964

  which are identical to the original patterns.

- Change the multiply with overflow so that we distinguish between signed and
  unsigned multiplication. Currently, unsigned multiplication with overflow
  isn't working!

llvm-svn: 60963

Fix add/sub expansion: don't create ADD / SUB with two results (seems like everyone is doing this these days :-). Patch by Daniel M Gessel!

llvm-svn: 60958

llvm-svn: 60951

do an extending load of the 4 bytes rather than a
potentially illegal (type) i32 load followed by a
sign extend.

llvm-svn: 60945

lowering f64 function arguments.

llvm-svn: 60944

Added support for TRUNC v8i16 to v8i8 for X86 (MMX)

llvm-svn: 60916

ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.

Similar for SUB and MUL instructions.

llvm-svn: 60915

llvm-svn: 60901

optimization of SGE/SLE with unit stride, now that it works properly.

llvm-svn: 60881

llvm-svn: 60875

llvm-svn: 60872

llvm-svn: 60869

llvm-svn: 60867

llvm-svn: 60866

vec_extract-sse4.ll.

llvm-svn: 60865

llvm-svn: 60861

them. The DAG combiner expects that nodes that are transformed have one value
result.

llvm-svn: 60857

llvm-svn: 60851

llvm-svn: 60850

Only perform SETO/SETC to JO/JC conversion if extractvalue is coming from an arithmetic with overflow instruction.

llvm-svn: 60844

for promoted integer types, eg: i16 on ppc-32, or
i24 on any platform.  Complete support for arbitrary
precision integers would require handling expanded
integer types, eg: i128, but I couldn't be bothered.

llvm-svn: 60834

causing a bunch of failures when running
"make ENABLE_EXPENSIVE_CHECKS=1 check".

llvm-svn: 60832

bit convert that changes the number of elements of a shuffle.

llvm-svn: 60829

Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin.

llvm-svn: 60828

llvm-svn: 60826

Fix a bug introduced by r59265. If lazy compilation is disabled, return actual function ptr instead of ptr to stub if function is already compiled.

llvm-svn: 60822

llvm-svn: 60821

parallel, allowing it to decide that P/Q must alias if A/B
must alias in things like:
 P = gep A, 0, i, 1
 Q = gep B, 0, i, 1

This allows GVN to delete 62 more instructions out of 403.gcc.

llvm-svn: 60820

llvm-svn: 60818

node latencies. Use CalcLatency instead of manual code in
CalculatePriorities to keep it consistent. Previously it
computed slightly different results.

llvm-svn: 60817

- Emit DW_AT_byte_size for struct and union of size zero.
- Emit DW_AT_declaration for forward type declaration.

llvm-svn: 60812

- Fix bug 3185, with misc other cleanups.
- Needed to implement SPUInstrInfo::InsertBranch(). CAUTION: Not sure what
  gets or needs to get passed to InsertBranch() to insert a conditional
  branch. This will abort for now until a good test case shows up.

llvm-svn: 60811

overflow/carry from the "arithmetic with overflow" intrinsics. It searches the
machine basic block from bottom to top to find the SETO/SETC instruction that is
its conditional. If an instruction modifies EFLAGS before it reaches the
SETO/SETC instruction, then it defaults to the normal instruction emission.

llvm-svn: 60807

The Cost field is removed. It was only being used in a very limited way,
to indicate when the scheduler should attempt to protect a live register,
and it isn't really needed to do that. If we ever want the scheduler to
start inserting copies in non-prohibitive situations, we'll have to
rethink some things anyway.

A Latency field is added. Instead of giving each node a single
fixed latency, each edge can have its own latency. This will eventually
be used to model various micro-architecture properties more accurately.

The PointerIntPair class and an internal union are now used, which
reduce the overall size.

llvm-svn: 60806

invalidateCachedPointerInfo.  Thanks to Bill for sending me
a testcase.

llvm-svn: 60805