llvm-svn: 146420

These modifiers simply select either the low or high D subregister of a Neon
Q register.  I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.

llvm-svn: 146417

llvm-svn: 146412

llvm-svn: 146411

llvm-svn: 146409

detected in the forward-CFG DFS. This prevents the reverse-CFG from
visiting blocks inside loops after blocks that dominate them in the
case where loops have multiple exits.

No testcase, because this fixes a bug which in practice only shows
up in a full optimizer run, due to the use-list order.

This fixes rdar://10422791 and others.

llvm-svn: 146408

llvm-svn: 146407

This computes the offset of the layout sucessor block, considering its
alignment as well.

llvm-svn: 146401

llvm-svn: 146400

llvm-svn: 146397

Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.

This is all gated by -arm-align-constant-islands.

llvm-svn: 146391

llvm-svn: 146389

llvm-svn: 146385

llvm-svn: 146384

llvm-svn: 146383

Also add an MCP member pointing to the machine constant pool.

No functional change intended.

llvm-svn: 146382

llvm-svn: 146380

llvm-svn: 146379

Original commit message:
Support/FileSystem: Implement canonicalize.

llvm-svn: 146378

llvm-svn: 146377

Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment.  When the command line
flag is set, also align the basic block containing the constant pool
entries.

This is only a partial implementation of constant island alignment. More
to come.

llvm-svn: 146375

a function to upgrade. Also, simplify the code a bit at the expense of
one line.

llvm-svn: 146368

llvm-svn: 146364

llvm-svn: 146363

llvm-svn: 146362

argument of the cttz and ctlz intrinsics.

llvm-svn: 146360

indicates whether the intrinsic has a defined result for a first
argument equal to zero. This will eventually allow these intrinsics to
accurately model the semantics of GCC's __builtin_ctz and __builtin_clz
and the X86 instructions (prior to AVX) which implement them.

This patch merely sets the stage by extending the signature of these
intrinsics and establishing auto-upgrade logic so that the old spelling
still works both in IR and in bitcode. The upgrade logic preserves the
existing (inefficient) semantics. This patch should not change any
behavior. CodeGen isn't updated because it can use the existing
semantics regardless of the flag's value.

Note that this will be followed by API updates to Clang and DragonEgg.

Reviewed by Nick Lewycky!

llvm-svn: 146357

The OptLevel is now redundant with the TargetMachine*.
And selectTarget() isn't really JIT-specific and could probably
get refactored into one of the lower level libraries.

llvm-svn: 146355

Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.

llvm-svn: 146344

Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.

llvm-svn: 146341

llvm-svn: 146340

of r146334!

llvm-svn: 146338

llvm-svn: 146335

the only parts of TM that depends on CodeGen headers with it.

llvm-svn: 146334

[fast-isel] SelectInsertValue seems to be causing miscompiles for ARM.  Disable while I investigate.

llvm-svn: 146331

Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.

llvm-svn: 146328

llvm-svn: 146327

Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.

llvm-svn: 146322

Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.

llvm-svn: 146318

The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.

This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.

<rdar://problem/10550705>

There is still an issue with correctly packing differently aligned
entries in the island.

llvm-svn: 146314