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  1. Jun 29, 2010
    • Bob Wilson's avatar
      Reapply my if-conversion cleanup from svn r106939 with fixes. · 1e5da550
      Bob Wilson authored
      There are 2 changes relative to the previous version of the patch:
      
      1) For the "simple" if-conversion case, there's no need to worry about
      RemoveExtraEdges not handling an unanalyzable branch.  Predicated terminators
      are ignored in this context, so RemoveExtraEdges does the right thing.
      This might break someday if we ever treat indirect branches (BRIND) as
      predicable, but for now, I just removed this part of the patch, because
      in the case where we do not add an unconditional branch, we rely on keeping
      the fall-through edge to CvtBBI (which is empty after this transformation).
      
      The change relative to the previous patch is:
      
      @@ -1036,10 +1036,6 @@
           IterIfcvt = false;
         }
       
      -  // RemoveExtraEdges won't work if the block has an unanalyzable branch,
      -  // which is typically the case for IfConvertSimple, so explicitly remove
      -  // CvtBBI as a successor.
      -  BBI.BB->removeSuccessor(CvtBBI->BB);
         RemoveExtraEdges(BBI);
       
         // Update block info. BB can be iteratively if-converted.
      
      
      2) My patch exposed a bug in the code for merging the tail of a "diamond",
      which had previously never been exercised.  The code was simply checking that
      the tail had a single predecessor, but there was a case in
      MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
      neither edge of the diamond.  I added the following change to check for
      that:
      
      @@ -1276,7 +1276,18 @@
         // tail, add a unconditional branch to it.
         if (TailBB) {
           BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
      -    if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
      +    bool CanMergeTail = !TailBBI.HasFallThrough;
      +    // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
      +    // check if there are any other predecessors besides those.
      +    unsigned NumPreds = TailBB->pred_size();
      +    if (NumPreds > 1)
      +      CanMergeTail = false;
      +    else if (NumPreds == 1 && CanMergeTail) {
      +      MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
      +      if (*PI != BBI1->BB && *PI != BBI2->BB)
      +        CanMergeTail = false;
      +    }
      +    if (CanMergeTail) {
             MergeBlocks(BBI, TailBBI);
             TailBBI.IsDone = true;
           } else {
      
      With these fixes, I was able to run all the SingleSource and MultiSource
      tests successfully.
      
      llvm-svn: 107110
      1e5da550
    • Dan Gohman's avatar
      Add an Intraprocedural form of BasicAliasAnalysis, which aims to · 0824affe
      Dan Gohman authored
      properly handles instructions and arguments defined in different
      functions, or across recursive function iterations.
      
      llvm-svn: 107109
      0824affe
    • Bruno Cardoso Lopes's avatar
      Described the missing AVX forms of SSE2 convert instructions · d6a091a4
      Bruno Cardoso Lopes authored
      llvm-svn: 107108
      d6a091a4
    • Bob Wilson's avatar
      Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is · 3d12ff79
      Bob Wilson authored
      the same as ARM except that the condition code field is always set to ARMCC::AL.
      
      llvm-svn: 107107
      3d12ff79
    • Bob Wilson's avatar
      Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they · 269a89fd
      Bob Wilson authored
      can't be changed arbitrarily by the DAGCombiner without checking if it is
      running after legalization.
      
      llvm-svn: 107097
      269a89fd
    • Bob Wilson's avatar
      Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead · 4469a892
      Bob Wilson authored
      of the Subtarget.
      
      llvm-svn: 107086
      4469a892
    • Devang Patel's avatar
      Use DW_FORM_addr for DW_AT_entry_pc. · 1de21ec4
      Devang Patel authored
      llvm-svn: 107085
      1de21ec4
    • Dale Johannesen's avatar
      In asm's, output operands with matching input constraints · 17feb07c
      Dale Johannesen authored
      have to be registers, per gcc documentation.  This affects
      the logic for determining what "g" should lower to.  PR 7393.
      A couple of existing testcases are affected.
      
      llvm-svn: 107079
      17feb07c
  2. Jun 28, 2010
  3. Jun 27, 2010
  4. Jun 26, 2010
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