objects for big endian and little endian targets.

Patch by Jack Carter.

llvm-svn: 151788

So with darwin's otool(1) an x86_64 hello world .o file will print:
leaq	L_.str(%rip), %rax ## literal pool for: Hello world

llvm-svn: 151769

Patch by Tyler Nowicki!

llvm-svn: 151743

llvm-svn: 151687

Without this hook, functions w/ a completely empty body (including no
epilogue) will cause an MCEmitter assertion failure.

For example,
define internal fastcc void @empty_function() {
  unreachable
}

rdar://10947471

llvm-svn: 151673

These instructions accept but do not require a size suffix.

rdar://10947225

llvm-svn: 151646

llvm-svn: 151645

llvm-svn: 151639

Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.

llvm-svn: 151630

llvm-svn: 151625

the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623

llvm-svn: 151615

llvm-svn: 151614

load and store instructions.

llvm-svn: 151611

When an outgoing call takes more than 2k of arguments on the stack, we
don't allocate that call frame in the prolog, but adjust the stack
pointer immediately before the call instead.

This causes problems with the emergency spill slot because PEI can't
track stack pointer adjustments on the second pass, and if the outgoing
arguments are too big, SP can't be used to reach the emergency spill
slot at all.

Work around these problems by ensuring there is a base or frame pointer
that can be used to access the emergency spill slot.

<rdar://problem/10917166>

llvm-svn: 151604

This patch adds instruction latencies for the SSE instructions
to the instruction scheduler for the Intel Atom.

llvm-svn: 151590

llvm-svn: 151582

We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.

To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.

rdar://10927209

llvm-svn: 151571

MCize function entry label emission on PowerPC64 properly.

llvm-svn: 151547

rdar://10921670
PR11935

llvm-svn: 151543

llvm-svn: 151540

llvm-svn: 151538

thumb instruction.  The PC adjustment is +4 in Thumb mode and +8 in ARM mode.

llvm-svn: 151530

Remove HexagonGenIntrinsics.inc from Hexagon cmake file. It does not appear in the Makefile and the output it produces isn't used. The Hexagon intrinsics are all in the global Intrinsics.gen.

llvm-svn: 151514

llvm-svn: 151512

llvm-svn: 151510

llvm-svn: 151473

Reverting this because it breaks static linking on ppc64. Specifically, it may be linkonce_odr functions that are the problem.
With this patch, if you link statically, calls to some functions end up calling their descriptor addresses instead
of calling to their entry points. This causes the execution to fail with SIGILL (b/c the descriptor address just
has some pointers, not code).

llvm-svn: 151433

Target/X86: Fix assertion failures and warnings caused by r151382 _ftol2 lowering for i386-*-win32 targets. Patch by Joe Groff.

[Joe Groff] Hi everyone. My previous patch applied as r151382 had a few problems:
Clang raised a warning, and X86 LowerOperation would assert out for
fptoui f64 to i32 because it improperly lowered to an illegal
BUILD_PAIR. Here's a patch that addresses these issues. Let me know if
any other changes are necessary. Thanks.

llvm-svn: 151432

add/sub instructions.

llvm-svn: 151415

reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register. 

example:

.cpload $25       // set $gp.
...
.cprestore 16     // store $gp to stack slot 16($sp).
...
jalr $25          // function call. clobbers $gp.
lw $gp, 16($sp)   // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25          // function call.
lw $gp, 16($sp)   // not emitted if $gp is not live after this instruction.
...

llvm-svn: 151402

llvm-svn: 151398

llvm-svn: 151384

used by the Win32 _ftol2 runtime function. Patch by Joe Groff!

llvm-svn: 151382

llvm-svn: 151374

Patch by Ahmed Charles

llvm-svn: 151360

Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics

llvm-svn: 151342

llvm-svn: 151341

llvm-svn: 151340

llvm-svn: 151339