llvm-svn: 76646

llvm-svn: 76645

llvm-svn: 76644

llvm-svn: 76643

llvm-svn: 76642

to SValuator::EvalCast. In the process, the StoreManagers now use this new cast
machinery, and the hack in GRExprEngine::EvalBind to handle implicit casts
involving OSAtomicCompareAndSwap and friends has been removed (and replaced with
logic closer to the logic specific to those functions).

llvm-svn: 76641

llvm-svn: 76640

llvm-svn: 76639

llvm-svn: 76638

llvm-svn: 76637

llvm-svn: 76636

llvm-svn: 76635

llvm-svn: 76634

be useful, and it's currently unused.  (Some issues: it isn't actually 
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)

llvm-svn: 76633

 - Patch by Jean-Daniel Dupas

llvm-svn: 76632

llvm-svn: 76631

1. Make it work correctly with anonymous unions.
2. Don't compute it if the warning isn't enabled.
3. Optimize the algorithm slightly to make it linear time in the 
case where we don't produce any warnings.

llvm-svn: 76630

llvm-svn: 76629

llvm-svn: 76628

llvm-svn: 76627

llvm-svn: 76626

llvm-svn: 76625

llvm-svn: 76624

llvm-svn: 76623

the declaration context, as occurs with out-of-line class template member
definitions.

llvm-svn: 76622

llvm-svn: 76621

llvm-svn: 76620

llvm-svn: 76619

llvm-svn: 76617

llvm-svn: 76616

Prefix IR dumps with LiveInterval indices when possible.  This turns
this:

	%ESI<def> = MOV32rr %EDI<kill>
	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	%reg1027<def> = MOVZX64rr32 %ESI
	%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
	%RDI<def> = MOV64rr %RSP
	%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
	%RSP<def> = MOV64rr %RDI

into this:

4	%reg1024<def> = MOV32rr %EDI<kill>
12	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20	%reg1025<def> = MOVZX64rr32 %reg1024
28	%reg1026<def> = MOV64rr %reg1025<kill>
36	%reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44	%reg1027<def> = MOV64rr %reg1026<kill>
52	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60	%reg1028<def> = MOV64rr %RSP
68	%reg1029<def> = MOV64rr %reg1028<kill>
76	%reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84	%RSP<def> = MOV64rr %reg1029

This helps greatly when debugging register allocation and coalescing
problems.

llvm-svn: 76615

llvm-svn: 76614

llvm-svn: 76613

llvm-svn: 76612

llvm-svn: 76611

llvm-svn: 76610

llvm-svn: 76609

llvm-svn: 76608

llvm-svn: 76607

llvm-svn: 76606