"On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment.

this patch disables .lcomm in favour of '.local .comm'

Patch by Kalle Raisklia!

llvm-svn: 100875

llvm-svn: 100815

merge XCore's section into MCSectionELF

llvm-svn: 100812

api and update clients to use MCContext instead.

llvm-svn: 100808

llvm-svn: 100762

llvm-svn: 100760

llvm-svn: 100758

llvm-svn: 100756

llvm-svn: 100751

Fixes PR3440.

llvm-svn: 100736

I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.

llvm-svn: 100735

llvm-svn: 100714

llvm-svn: 100709

llvm-svn: 100706

llvm-svn: 100697

llvm-svn: 100696

Next to work on is ARMDisassemblerCore.cpp.

llvm-svn: 100695

argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.

llvm-svn: 100694

llvm-svn: 100693

ARMDecoderEmitter.cpp, with FIXME comment.

llvm-svn: 100690

a simple mapping of register names to IDs to
identify register tokens.

llvm-svn: 100685

DBG_VALUE does not generate code.

llvm-svn: 100681

It is not ready for public yet.

llvm-svn: 100673

llvm-svn: 100672

llvm-svn: 100671

llvm-svn: 100670

llvm-svn: 100669

llvm-svn: 100668

llvm-svn: 100667

llvm-svn: 100666

llvm-svn: 100665

llvm-svn: 100664

llvm-svn: 100663

llvm-svn: 100662

llvm-svn: 100661

llvm-svn: 100660

llvm-svn: 100659

llvm-svn: 100658

llvm-svn: 100657

llvm-svn: 100656