"On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment.

this patch disables .lcomm in favour of '.local .comm'

Patch by Kalle Raisklia!

llvm-svn: 100875

llvm-svn: 100860

%RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>

llvm-svn: 100804

llvm-svn: 100751

ensure that the expansion is dominated by the increments of those loops.

llvm-svn: 100748

llvm-svn: 100705

explicitly split into stride-and-offset pairs. Also, add the
ability to track multiple post-increment loops on the same expression.

This refines the concept of "normalizing" SCEV expressions used for
to post-increment uses, and introduces a dedicated utility routine for
normalizing and denormalizing expressions.

This fixes the expansion of expressions which are post-increment users
of more than one loop at a time. More broadly, this takes LSR another
step closer to being able to reason about more than one loop at a time.

llvm-svn: 100699

those who don't build all targets.

llvm-svn: 100688

llvm-svn: 100637

MachineOperand::isIdenticalTo wasn't handling metadata operands.

llvm-svn: 100636

llvm-svn: 100612

This fixes the Bullet regression on i386/nocona.

llvm-svn: 100553

llvm-svn: 100482

llvm-svn: 100455

llvm-svn: 100346

llvm-svn: 100208

in particular, they end up aligning strings at 16-byte boundaries, and
there's no way for GlobalOpt to check OptForSize.

llvm-svn: 100172

After trivial coalescing, the MI being visited may have become a copy. Avoid adding it to CSE hash table since copies aren't being considered for CSE and they may be deleted.
rdar://7819990

llvm-svn: 100170

unaligned loads into aligned loads.

llvm-svn: 100166

llvm-svn: 100165

llvm-svn: 100137

- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.

llvm-svn: 100118

llvm-svn: 100101

1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
   load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
   ops more effectively.
rdar://7774704

llvm-svn: 100090

llvm-svn: 99975

llvm-svn: 99974

llvm-svn: 99959

llvm-svn: 99954

Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.

llvm-svn: 99910

to be fixed any time soon.

llvm-svn: 99888

llvm-svn: 99840

"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions:
-in vararg handling, registers are marked to be live, to not confuse the register scavenger
-function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack."

llvm-svn: 99819

transforming it into (add (i32 GPR), 4).  This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align.  This allows us to fold an extra load
in the changed testcase.

llvm-svn: 99756

llvm-svn: 99752

llvm-svn: 99751

llvm-svn: 99620

llvm-svn: 99598

Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register.

llvm-svn: 99575

Re-commit. This time complete with testsuite updates.

llvm-svn: 99570

llvm-svn: 99546