llvm-svn: 105375

instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

  %reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

  %reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

llvm-svn: 105358

llvm-svn: 105350

llvm-svn: 105344

backend.  Add a FIXME noting what can be fixed here.

llvm-svn: 105342

mailing list archives.

llvm-svn: 105341

and tidy up the comment describing it.

llvm-svn: 105339

llvm-svn: 105335

llvm-svn: 105325

llvm-svn: 105322

backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.

llvm-svn: 105321

x86 backend currently doesn't know how to handle them.

This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either.  We do get a better error message, though.

llvm-svn: 105305

llvm-svn: 105303

in X86FastISel. Patch by Jan Sjodin.

llvm-svn: 105290

llvm-svn: 105276

llvm-svn: 105269

llvm-svn: 105109

llvm-svn: 105108

llvm-svn: 105107

llvm-svn: 105106

Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.

llvm-svn: 105092

were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063

Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.

llvm-svn: 105060

llvm-svn: 105059

llvm-svn: 105014

llvm-svn: 105005

llvm-svn: 105001

getX86RegNum() does not happen.  Patch by Shantonu Sen!

llvm-svn: 104994

llvm-svn: 104980

llvm-svn: 104974

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.

llvm-svn: 104907

an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900

llvm-svn: 104899

llvm-svn: 104897

llvm-svn: 104891

llvm-svn: 104890

should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.

llvm-svn: 104883

No functional effect as these nodes are not generated yet.

llvm-svn: 104879

To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.

llvm-svn: 104866