Substantial SelectionDAG scheduling is going away soon, and is
interfering with Hao's attempts to implement LDn/STn instructions, so
I say we make the leap first.

There were a few reorderings (inevitably) which broke some tests. I
tried to replace them with CHECK-DAG variants mostly, but some too
complex for that to be useful and I just reordered them.

llvm-svn: 192282

This was only working because AVX had cheaper rules in all cases.
I'm sure there are other places in this file where predicates are missing.

llvm-svn: 192276

Replace a couple instructions with patterns referring to other instructions with same encoding and operands. Mark a couple other instructions as CodeGenOnly since we have FR and VR instructions and only one of them is needed by the assembler/disassembler.

llvm-svn: 192274

Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB prefix and keeps the mnemonic from starting with an extra 'v'

llvm-svn: 192272

Mark some instructions as CodeGenOnly since they aren't needed by the assembler or disassembler. Disassembler already filtered them, but asm parser still had them in its tables.

llvm-svn: 192271

Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size.

llvm-svn: 192266

to use DIScopeRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192256

typedef are updated to use DIScopeRef.

llvm-svn: 192254

is updated to use DITypeRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192251

is updated to use DITypeRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192246

reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192242

convert instructions.

llvm-svn: 192231

This fixes repeated -Wmicrosoft warnings when self-hosting clang on
Windows, and gets us real unsigned enum types with MSVC.

llvm-svn: 192227

Mips16 will try and create a stub for it and this will
result in a link error because that function does not exist in libc.

llvm-svn: 192223

llvm-svn: 192218

llvm-svn: 192216

llvm-svn: 192215

No intended functionality change.

llvm-svn: 192213

have native instructions for this.

llvm-svn: 192207

llvm-svn: 192199

Patch by Vladimir Voskresensky. The erros were:

Path.inc:274:3: error: ‘Dl_info’ was not declared in this scope
...

and

usr/include/spawn.h:52:14: error: expected ‘,’ or ‘...’ before ‘argv’

llvm-svn: 192185

This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.

The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.

I will send an email to llvmdev with instructions on how to use this.

llvm-svn: 192181

llvm-svn: 192179

llvm-svn: 192178

No new testcases. However, this patch makes all supported JIT testcases in 
test/ExecutionEngine  pass on Sparc.

llvm-svn: 192176

Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building.

llvm-svn: 192175

Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.

llvm-svn: 192171

[Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead.

llvm-svn: 192160

This is ever-so faster but more importantly matches what we have elsewhere.

llvm-svn: 192137

Otherwise, we don't perform operations that would have been performed on
the scalar version.

Fixes PR17498.

llvm-svn: 192133

llvm-svn: 192130

from struct byval to registers.

We used to pass 0 which means the alignment of PtrVT. Even when the alignment
of the struct is smaller than 4, the LOADs would have alignment of 4, and
further optimizations could combine the LOADs into a ldm, which would
cause crash.

The fix is to pass the alignment of the struct byval.

rdar://problem/15144402

llvm-svn: 192126

llvm-svn: 192125

llvm-svn: 192124

Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

llvm-svn: 192123

llvm-svn: 192122

llvm-svn: 192121

accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.

llvm-svn: 192119

llvm-svn: 192118

Bitcasting everything to i8* won't work. Autoupgrade the old
intrinsic declarations to use the new mangling.

llvm-svn: 192117