llvm-svn: 134734

llvm-svn: 134732

llvm-svn: 134730

llvm-svn: 134729

Fix a FIXME.

llvm-svn: 134727

llvm-svn: 134725

llvm-svn: 134721

llvm-svn: 134720

llvm-svn: 134719

No functional change.

llvm-svn: 134714

TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712

llvm-svn: 134709

llvm-svn: 134708

llvm-svn: 134707

Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705

This allows the (many) pseudo-instructions we have that map onto a single
real instruction to have their expansion during MC lowering handled
automatically instead of the current cumbersome manual expansion required.
These sorts of pseudos are common when an instruction is used in situations
that require different MachineInstr flags (isTerminator, isBranch, et. al.)
than the generic instruction description has. For example, using a move
to the PC to implement a branch.

llvm-svn: 134704

llvm-svn: 134703

llvm-svn: 134702

Should fix llvm-gcc selfhost.

llvm-svn: 134699

llvm-svn: 134696

We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

  struct foo { char x[24]; };
  long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  sarl	$3, %eax
  imull	$-1431655765, %eax, %eax
instead of
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  movl	$715827883, %ecx
  imull	%ecx
  movl	%edx, %eax
  shrl	$31, %eax
  sarl	$2, %edx
  addl	%eax, %edx
  movl	%edx, %eax

llvm-svn: 134695

- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678

Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics.

llvm-svn: 134677

llvm-svn: 134671

llvm-svn: 134668

llvm-svn: 134667

It was testing a linear scan feature:

  Test if linearscan is unfavoring registers for allocation to allow
  more reuse of reloads from stack slots.

The greedy register allocator doesn't access any stack slots in this
function, so the linear scan feature was not being tested.

llvm-svn: 134666

Fixes PR9602!

llvm-svn: 134665

processor supports it just fine.

Fixes PR9675 and rdar://9740801

llvm-svn: 134664

llvm-svn: 134661

llvm-svn: 134658

Part of PR10299 and rdar://9740322

llvm-svn: 134653

Fixes PR10149 and rdar://9738585

llvm-svn: 134648

llvm-svn: 134647

llvm-svn: 134645

llvm-svn: 134643

llvm-svn: 134641

llvm-svn: 134640

based on a modifier, split it into two functions.

llvm-svn: 134637

numbers should be printed instead of symbolic register names in
MCAsmStreamer::EmitRegisterName. This is necessary because some versions of
GNU assembler won't accept code in which symbolic register names are used in
cfi directives. There is no change in behavior unless the flag is explicitly
set to true by a backend.

llvm-svn: 134635