llvm-svn: 150653

Don't attempt to move instructions with regmask operands. They are most
likely calls anyway.

llvm-svn: 150634

The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface.

llvm-svn: 150633

llvm-svn: 150630

llvm-svn: 150628

llvm-svn: 150627

method. This allows the target lowering code to not have to deal with MDNodes.

Also, avoid leaking memory like a sieve by not creating a global variable for
the image info section, but just emitting the code directly.

llvm-svn: 150624

llvm-svn: 150619

llvm-svn: 150608

Patch by Sundeep!

llvm-svn: 150607

I'll put MachineLICM back before PEI. All my arm/x86 benchmarks look good, but buildbots don't like it.

llvm-svn: 150568

llvm-svn: 150567

llvm-svn: 150566

llvm-svn: 150565

The llc command line options for enabling/disabling passes are local to CodeGen/Passes.cpp. This patch associates those options with standard pass IDs so they work regardless of how the target configures the passes.

A target has two ways of overriding standard passes:
1) Redefine the pass pipeline (override TargetPassConfig::add%Stage)
2) Replace or suppress individiual passes with TargetPassConfig::substitutePass.

In both cases, the command line options associated with the pass override the target default.

For example, say a target wants to disable machine instruction scheduling by default:

- The target calls disablePass(MachineSchedulerID) but otherwise does not override any TargetPassConfig methods.

- Without any llc options, no scheduler is run.

- With -enable-misched, the standard machine scheduler is run and honors the -misched=... flag to select the scheduler variant, which may be used for performance evaluation or testing.

Sorry overridePass is ugly. I haven't thought of a better way without replacing the cl::opt framework. I hope to do that one day...

I haven't figured out why CodeGen uses char& for pass IDs. AnalysisID is much easier to use and less bug prone. I'm using it wherever I can for internal implementation. Maybe later we can change the global pass ID definitions as well.

llvm-svn: 150563

Added TargetPassConfig::disablePass/substitutePass as a general mechanism to override specific passes.

llvm-svn: 150562

llvm-svn: 150553

llvm-svn: 150552

llvm-svn: 150550

Pretend that regmask interference ends at the 'dead' slot, even when
there is other interference ending at the 'reg' slot of the same
instruction.

llvm-svn: 150531

Perform all comparisons at instruction granularity, and make sure
register masks on uses count in both gaps.

llvm-svn: 150530

Only accept register masks when looking for an 'overlapping' def. When
Overlap is not set, the function searches for a proper definition of
Reg.

This means MI->modifiesRegister() considers register masks, but
MI->definesRegister() doesn't.

llvm-svn: 150529

When a physreg is live in to a basic block, look for any instruction in
the block that clobbers the physreg.

The instruction doesn't have to properly redefine the register, any
overlapping clobber is OK.

This slightly changes live ranges when compiling with register masks.

llvm-svn: 150528

The old DenseMap hashed order was very confusing.

llvm-svn: 150527

llvm-svn: 150525

The MachO back-end needs to emit the garbage collection flags specified in the
module flags. This is a WIP, so the front-end hasn't been modified to emit these
flags just yet. Documentation and front-end switching to occur soon.

llvm-svn: 150507

llvm-svn: 150496

only be live in to a block if it is the function entry point or a landing pad.

llvm-svn: 150494

that are greater than the vector element type. For example BUILD_VECTOR
of type <1 x i1> with a constant i8 operand.
This patch fixes the assertion.

llvm-svn: 150477

llvm-svn: 150471

Rename getExceptionAddressRegister() to getExceptionPointerRegister() for consistency with setExceptionPointerRegister(...).

llvm-svn: 150460

llvm-svn: 150457

marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.

llvm-svn: 150437

llvm-svn: 150436

The scheduler will sometimes check the implicit-def list on instructions
to properly handle pre-colored DAG edges.

Also check any register mask operands for physreg clobbers.

llvm-svn: 150428

llvm-svn: 150411

llvm-svn: 150404

Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant generate a shuffle node from two vectors of different types.

llvm-svn: 150383

This patch addresses the problem of poor code generation for the zext
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes.
The DAGCombiner has two optimizations that can mitigate the problem. First,
if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT
nodes, then it is possible to create a new simplified BUILD_VECTOR which uses
UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes.
Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle
vector instruction.

In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be
shuffled into a wide YMM register.

This patch modifes the second optimization and allows the creation of
shuffle vectors even when the newly generated vector and the original vector
from which we extract the values are of different types.

llvm-svn: 150340

Patch by Kai Nacke!

llvm-svn: 150307