Commits · 20d73c6cc0e0010edd5e3239b78225388380f0d6 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Jul 22, 2015
- [BranchFolding] do not iterate the aliases of virtual registers · 20d73c6c
  Jingyue Wu authored Jul 22, 2015
  20d73c6c
- [SROA] Fix a nasty pile of bugs to do with big-endian, different alloca · ccffdaf7
  Chandler Carruth authored Jul 22, 2015
  ccffdaf7
- [dsymutil] Implement ODR uniquing for C++ code. · 1c65094d
  Frederic Riss authored Jul 21, 2015
  1c65094d
- MIR Serialization: Start serializing the CFI operands with .cfi_def_cfa_offset. · f4baeb51
  Alex Lorenz authored Jul 21, 2015
  f4baeb51
Jul 21, 2015
- [MDA] change BlockScanLimit into a command line option. · d058ea92
  Jingyue Wu authored Jul 21, 2015
  d058ea92
- [AsmPrinter] Check for valid constants in handleIndirectSymViaGOTPCRel · e8640518
  Bruno Cardoso Lopes authored Jul 21, 2015
  e8640518
- [Object][ELF] Handle files with no section header string table. · 402a4f10
  Michael J. Spencer authored Jul 21, 2015
  402a4f10
- [PPC64LE] More vector swap optimization TLC · 2be8054b
  Bill Schmidt authored Jul 21, 2015
  2be8054b
- Re-land 242726 to use RAII to do cleanup · 2f907557
  Reid Kleckner authored Jul 21, 2015
  2f907557
- MergeFunc: Transfer the callee's attributes when replacing a direct caller · 36512330
  Arnold Schwaighofer authored Jul 21, 2015
  36512330
- MIR Serialization: Serialize the external symbol machine operands. · 6ede3744
  Alex Lorenz authored Jul 21, 2015
  6ede3744
- Revert 242726, it broke ASan on OS X. · f00afcc7
  Nico Weber authored Jul 21, 2015
  f00afcc7
- Constfold trunc,rint,nearbyint,ceil and floor using APFloat · d818e38f
  Karthik Bhat authored Jul 21, 2015
  d818e38f
- AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , · f7fd547e
  Igor Breger authored Jul 21, 2015
  f7fd547e
- [ARM] Define subtarget feature "reserve-r9", which is used to decide · 28581525
  Akira Hatanaka authored Jul 21, 2015
  28581525
- ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code · a50d2203
  Matthias Braun authored Jul 21, 2015
  a50d2203
- ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 · e40d89ef
  Matthias Braun authored Jul 21, 2015
  e40d89ef
- Revert r242737. · 42427d2c
  Akira Hatanaka authored Jul 20, 2015
  42427d2c
- [ARM] Define subtarget feature "reserve-r9", which is used to decide · 7482d40c
  Akira Hatanaka authored Jul 20, 2015
  7482d40c
- Revert "ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2" · 731e359e
  Matthias Braun authored Jul 20, 2015
  731e359e
- Revert "ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code" · 84e28970
  Matthias Braun authored Jul 20, 2015
  84e28970
- Targets: commonize some stack realignment code · e4d22d59
  JF Bastien authored Jul 20, 2015
  e4d22d59
- Don't try to instrument allocas used by outlined SEH funclets · 87d03450
  Reid Kleckner authored Jul 20, 2015
  87d03450
- AArch64: Add aditional Cyclone macroop fusion opportunities · e536f4f6
  Matthias Braun authored Jul 20, 2015
  e536f4f6
- MachineScheduler: Restrict macroop fusion to data-dependent instructions. · 2bd6dd8d
  Matthias Braun authored Jul 20, 2015
  2bd6dd8d
Jul 20, 2015
- [ARM] Refactor the prologue/epilogue emission to be more robust. · 71a71485
  Quentin Colombet authored Jul 20, 2015
  71a71485
- [NVPTX] make load on global readonly memory to use ldg · 48a9bdc6
  Jingyue Wu authored Jul 20, 2015
  48a9bdc6
- Simplify iterating over the dynamic section and report broken ones. · b68a16c4
  Rafael Espindola authored Jul 20, 2015
  b68a16c4
- [Hexagon] Generate MUX from conditional transfers when dot-new not possible · 92172204
  Krzysztof Parzyszek authored Jul 20, 2015
  92172204
- MIR Serialization: Initial serialization of machine constant pools. · ab980499
  Alex Lorenz authored Jul 20, 2015
  ab980499
- [ImplicitNullChecks] Work with implicit defs. · 93d608c3
  Sanjoy Das authored Jul 20, 2015
  93d608c3
- MIR Parser: Add support for quoted named global value operands. · b29554da
  Alex Lorenz authored Jul 20, 2015
  b29554da
- Remove Elf_Rela_Iter and Elf_Rel_Iter. · 33f25093
  Rafael Espindola authored Jul 20, 2015
  33f25093
- [AArch64] Change EON pattern to match more often. · 3da0ea7f
  Chad Rosier authored Jul 20, 2015
  3da0ea7f
- Add missing test for r242296 (vec_sld) · 19dbd6c6
  Bill Schmidt authored Jul 20, 2015
  19dbd6c6
- Report errors an invalid virtual addresses. · 836f2e86
  Rafael Espindola authored Jul 20, 2015
  836f2e86
- AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops · 70580f83
  Tom Stellard authored Jul 20, 2015
  70580f83
- Simplify iterating over program headers and detect corrupt ones. · 073624bb
  Rafael Espindola authored Jul 20, 2015
  073624bb
- [mips] Added support for the ERETNC instruction. · 974d4092
  Vasileios Kalintiris authored Jul 20, 2015
  974d4092
- llvm-readobj: Handle invalid references to the string table. · 00ddb141
  Rafael Espindola authored Jul 20, 2015
  00ddb141