llvm-svn: 140947

llvm-svn: 140946

llvm-svn: 140943

llvm-svn: 140942

llvm-svn: 140941

llvm-svn: 140940

llvm-svn: 140939

Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.

llvm-svn: 140938

llvm-svn: 140937

and block addresses.

llvm-svn: 140936

* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.

llvm-svn: 140935

llvm-svn: 140934

pool value.

It's not used right now, but will be soon.

llvm-svn: 140933

llvm-svn: 140928

useful if an optimization assumes the stack has been realigned.  Credit to
Eli for his assistance.
rdar://10043857

llvm-svn: 140924

We want heuristics to be based on accurate data, but more importantly
we don't want llvm to behave randomly. A benign trunc inserted by an
upstream pass should not cause a wild swings in optimization
level. See PR11034. It's a general problem with threshold-based
heuristics, but we can make it less bad.

llvm-svn: 140919

llvm-svn: 140916

llvm-svn: 140906

All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905

llvm-svn: 140904

llvm-svn: 140903

and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.

For instance, in file A.c:

   struct S s;

In file B.c:
   struct {
     // something long
   };
   extern S s;

   void foo() {
     struct S p = s;
     // ...
   }

this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.

llvm-svn: 140902

llvm-svn: 140899

This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898

This one can also print 32-bit groups.

llvm-svn: 140897

It will soon need the context.

llvm-svn: 140896

Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895

llvm-svn: 140892

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140891

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140887

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140886

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140885

Test of indexing lists of lists of lists works.  This also exercises
some operators.

llvm-svn: 140884

Add a TableGen test to check if indexing lists of lists works.

llvm-svn: 140883

Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

llvm-svn: 140882

llvm-svn: 140879

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140878

llvm-svn: 140875

llvm-svn: 140874

llvm-svn: 140873