- Apr 08, 2010
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Chris Lattner authored
llvm-svn: 100709
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Chris Lattner authored
llvm-svn: 100706
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Chris Lattner authored
llvm-svn: 100703
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Chris Lattner authored
llvm-svn: 100702
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Chris Lattner authored
llvm-svn: 100700
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Dan Gohman authored
explicitly split into stride-and-offset pairs. Also, add the ability to track multiple post-increment loops on the same expression. This refines the concept of "normalizing" SCEV expressions used for to post-increment uses, and introduces a dedicated utility routine for normalizing and denormalizing expressions. This fixes the expansion of expressions which are post-increment users of more than one loop at a time. More broadly, this takes LSR another step closer to being able to reason about more than one loop at a time. llvm-svn: 100699
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Johnny Chen authored
llvm-svn: 100697
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Johnny Chen authored
llvm-svn: 100696
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- Apr 07, 2010
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Johnny Chen authored
Next to work on is ARMDisassemblerCore.cpp. llvm-svn: 100695
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Sean Callanan authored
argument that had to be between 0 and 7 to have any value, firing an assert later in the AsmPrinter. Now, the disassembler rejects instructions with out-of-range values for that immediate. llvm-svn: 100694
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Johnny Chen authored
llvm-svn: 100693
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Johnny Chen authored
ARMDecoderEmitter.cpp, with FIXME comment. llvm-svn: 100690
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Sean Callanan authored
a simple mapping of register names to IDs to identify register tokens. llvm-svn: 100685
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Dale Johannesen authored
DBG_VALUE does not generate code. llvm-svn: 100681
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Gabor Greif authored
llvm-svn: 100677
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Anton Korobeynikov authored
It is not ready for public yet. llvm-svn: 100673
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Anton Korobeynikov authored
llvm-svn: 100672
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Anton Korobeynikov authored
llvm-svn: 100671
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Anton Korobeynikov authored
llvm-svn: 100670
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Anton Korobeynikov authored
llvm-svn: 100669
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Anton Korobeynikov authored
llvm-svn: 100668
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Anton Korobeynikov authored
llvm-svn: 100667
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Anton Korobeynikov authored
llvm-svn: 100666
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Anton Korobeynikov authored
llvm-svn: 100665
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Anton Korobeynikov authored
llvm-svn: 100664
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Anton Korobeynikov authored
llvm-svn: 100663
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Anton Korobeynikov authored
llvm-svn: 100662
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Anton Korobeynikov authored
llvm-svn: 100661
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Anton Korobeynikov authored
llvm-svn: 100660
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Anton Korobeynikov authored
llvm-svn: 100659
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Anton Korobeynikov authored
llvm-svn: 100658
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Anton Korobeynikov authored
llvm-svn: 100657
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Anton Korobeynikov authored
llvm-svn: 100656
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Anton Korobeynikov authored
llvm-svn: 100655
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Anton Korobeynikov authored
llvm-svn: 100654
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Anton Korobeynikov authored
llvm-svn: 100653
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Anton Korobeynikov authored
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. llvm-svn: 100652
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Anton Korobeynikov authored
llvm-svn: 100651
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Anton Korobeynikov authored
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
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Anton Korobeynikov authored
llvm-svn: 100649
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