Vector selects are cheap on NEON. They get lowered to a vbsl instruction.

radar://13158753

llvm-svn: 174631

22 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174615

Excuse me, I could not test it locally.

llvm-svn: 174614

Use sub0-15 everywhere.

Patch by: Michel Dänzerr

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 174610

These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

llvm-svn: 174609

All of the le and lt variants are unsupported.

llvm-svn: 174608

llvm-svn: 174607

llvm-svn: 174602

llvm-svn: 174591

llvm-svn: 174588

llvm-svn: 174587

llvm-svn: 174586

llvm-svn: 174585

For example, when we are doing mips16 hard float or soft float.

llvm-svn: 174583

A double inclusion will pretty much always be an error in TableGen, so
there's no point going on just to die with "def already defined" or
whatnot.

I'm not too thrilled about the "public: ... private: ..." to expose the
DependenciesMapTy, but I really didn't see a better way to keep that
type centralized. It's a smell that indicates that some refactoring is
needed to make this code more loosely coupled.

This should avoid all bugs of the same nature as PR15189.

llvm-svn: 174582

1. Moved a comment from ObjCARCOpts.cpp -> ObjCARCContract.cpp.
2. Removed a comment from ObjCARCOpts.cpp that was already moved to
ObjCARCAliasAnalysis.h/.cpp.

llvm-svn: 174581

llvm-svn: 174580

FIXME: Are they really truncated to i32 from i64 unconditionally?
llvm-svn: 174574

llvm-svn: 174572

llvm-svn: 174571

llvm-svn: 174569

llvm-svn: 174568

llvm-svn: 174566

Fix CMake detection of various cmath functions, and XFAIL the test on platforms that are known to be missing them.

llvm-svn: 174564

Conditionalize constant folding of math intrinsics on the availability of an implementation on the host.  This is a little bit unfortunate, but until someone decides to implement a full libm for APFloat, we don't have a better way to get this functionality.

llvm-svn: 174561

Signficantly generalize our ability to constant fold floating point intrinsics, including ones on half types.

llvm-svn: 174555

llvm-svn: 174553

Thanks to Andrew, David, and Aaron for helping fix this.

llvm-svn: 174552

file was generated.

llvm-svn: 174551

llvm-svn: 174550

units coming in.

llvm-svn: 174548

llvm-svn: 174547

llvm-svn: 174546

The test is a binary placed in test/DebugInfo/Inputs, with a source C
file used for reference/reproducing. The source's first line is a clang
build command for reproducing the binary.

llvm-svn: 174543

account. Atoms use LEA for updating SP in prologs/epilogs, and the
exact LEA opcode depends on the data model.

Also reapplying the test case which was added and then reverted
(because of Atom failures), this time specifying explicitly the CPU in
addition to the triple. The test case now checks all variations (data
mode, cpu Atom vs. Core).

llvm-svn: 174542

Canonicalize line endings to Linux style also when the --strict-whitespace flag is in use. This flag is supposed to affect horizontal whitespaces only.

llvm-svn: 174541

llvm-svn: 174536

Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI.  Rename
things to clarify this.  Also delete some code that's been commented out
for a long time.

llvm-svn: 174526

Only implemented for R600 so far.  SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.

At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.

v2:
  - Add support for i8 zext load from stack.
  - Coding style fixes

v3:
  - Don't reserve registers for indirect addressing when it isn't
    being used.
  - Fix bug caused by LLVM limiting the number of SubRegIndex
    declarations.

v4:
  - Fix 64-bit defines

llvm-svn: 174525

Weakly defined symbols should evaluate to 0 if they're undefined at
link-time. This is impossible to do with the usual address generation
patterns, so we should use a literal pool entry to materlialise the
address.

llvm-svn: 174518