llvm-svn: 13956

llvm-svn: 13910

spills. This allows for more flexibility when allocating registers for
spill code.

llvm-svn: 13907

llvm-svn: 13892

llvm-svn: 13416

workaround, use the C HUGE_VAL macro instead.

llvm-svn: 13377

llvm-svn: 13302

llvm-svn: 12872

llvm-svn: 12869

llvm-svn: 12866

llvm-svn: 12791

instruction to make the API more flexible.

llvm-svn: 12386

llvm-svn: 12058

MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.

llvm-svn: 11882

llvm-svn: 11721

llvm-svn: 11719

llvm-svn: 11704

Also make it less aggressive as the current implementation breaks in
some cases.

llvm-svn: 11696

llvm-svn: 11687

llvm-svn: 11676

llvm-svn: 11675

llvm-svn: 11674

1. LiveIntervals now implement a 4 slot per instruction model. Load,
   Use, Def and a Store slot. This is required in order to correctly
   represent caller saved register clobbering on function calls,
   register reuse in the same instruction (def resues last use) and
   also spill code added later by the allocator. The previous
   representation (2 slots per instruction) was insufficient and as a
   result was causing subtle bugs.

2. Fixes in spill code generation. This was the major cause of
   failures in the test suite.

3. Linear scan now has core support for folding memory operands. This
   is untested and not enabled (the live interval update function does
   not attempt to fold loads/stores in instructions).

4. Lots of improvements in the debugging output of both live intervals
   and linear scan. Give it a try... it is beautiful :-)

In summary the above fixes all the issues with the recent reserved
register elimination changes and get the allocator very close to the
next big step: folding memory operands.

llvm-svn: 11654

llvm-svn: 11575

llvm-svn: 11574

llvm-svn: 11516

llvm-svn: 11476

std::numeric_limits<float>::max() for weighting preallocated
intervals.

llvm-svn: 11427

llvm-svn: 11393

ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340

llvm-svn: 11283

slots each. As a concequence they get numbered as 0, 2, 4 and so
on. The first slot is used for operand uses and the second for
defs. Here's an example:

0: A = ...
2: B = ...
4: C = A + B ;; last use of A

The live intervals should look like:

A = [1, 5)
B = [3, x)
C = [5, y)

llvm-svn: 11141

access. Rather we only have to do it on the creation of the interval.

llvm-svn: 11135

outside of loops = 0.

llvm-svn: 11085

llvm-svn: 11057

llvm-svn: 11054

llvm-svn: 11048

llvm-svn: 11047

MRegisterInfo::isVirtualRegister.

llvm-svn: 11045

llvm-svn: 11040