Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711

llvm-svn: 137707

llvm-svn: 137706

Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.

llvm-svn: 137686

also add the AVX versions of the 128-bit patterns

llvm-svn: 137685

predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

llvm-svn: 137684

Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675

when AVX mode is one. Otherwise is just more work for the type
legalizer.

llvm-svn: 137661

Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode.  Update tests to reflect this fact.
Patch by James Molloy.

llvm-svn: 137647

llvm-svn: 137643

llvm-svn: 137641

llvm-svn: 137636

Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.

llvm-svn: 137635

llvm-svn: 137615

Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551

Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.

rdar://9945172

llvm-svn: 137525

llvm-svn: 137521

vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

llvm-svn: 137519

llvm-svn: 137518

llvm-svn: 137515

Partial fix for rdar://9945172.

llvm-svn: 137513

Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.

llvm-svn: 137502

llvm-svn: 137499

Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.

llvm-svn: 137494

llvm-svn: 137487

integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.

- In the test case, the following code is generated before this patch is
  applied:
mtc1  $zero, $f2    ; unformatted copy to $f2
mov.s $f0, $f2      ; $f0 is in single format
sdc1  $f12, 0($sp)
mov.s $f1, $f2      ; $f1 is in single format
c.eq.d  $f12, $f0   ; $f0 cannot be interpreted as double

- The following code is generated after this patch is applied:
mtc1  $zero, $f0    ; unformatted copy to $f0
mtc1  $zero, $f1    ; unformatted copy to $f1
c.eq.d  $f12, $f0   ; $f0 can be interpreted as double

Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.

llvm-svn: 137484

llvm-svn: 137481

llvm-svn: 137476

when building with assertions disabled.

llvm-svn: 137460

Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.

llvm-svn: 137404

llvm-svn: 137389

warning. 

llvm-svn: 137378

llvm-svn: 137375

llvm-svn: 137372

llvm-svn: 137371

llvm-svn: 137370

llvm-svn: 137368

llvm-svn: 137367

llvm-svn: 137364

llvm-svn: 137363