- Mar 01, 2014
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Venkatraman Govindaraju authored
llvm-svn: 202599
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Venkatraman Govindaraju authored
llvm-svn: 202598
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Venkatraman Govindaraju authored
llvm-svn: 202597
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Sasa Stankovic authored
llvm-svn: 202594
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Venkatraman Govindaraju authored
llvm-svn: 202581
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Venkatraman Govindaraju authored
llvm-svn: 202578
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Venkatraman Govindaraju authored
llvm-svn: 202577
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Venkatraman Govindaraju authored
llvm-svn: 202575
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Venkatraman Govindaraju authored
llvm-svn: 202573
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Venkatraman Govindaraju authored
llvm-svn: 202572
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Venkatraman Govindaraju authored
llvm-svn: 202571
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Venkatraman Govindaraju authored
llvm-svn: 202564
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Venkatraman Govindaraju authored
[Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code. llvm-svn: 202563
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Manman Ren authored
Inside iterate, we scan backwards then scan forwards in a loop. When iteration is not zero, the last node was just updated so we can skip it. But when iteration is zero, we can't skip the last node. For the testing case, fixing this will save a spill and move register copies from hot path to cold path. llvm-svn: 202557
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- Feb 28, 2014
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Tom Stellard authored
llvm-svn: 202543
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Justin Bogner authored
Tools that use the CommandLine library currently exit with an error when invoked with -version or -help. This is unusual and non-standard, so we'll fix them to exit successfully instead. I don't expect that anyone relies on the current behaviour, so this should be a fairly safe change. llvm-svn: 202530
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Adam Nemet authored
llvm-svn: 202528
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Zoran Jovanovic authored
llvm-svn: 202526
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Zoran Jovanovic authored
llvm-svn: 202523
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Zoran Jovanovic authored
llvm-svn: 202521
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Zoran Jovanovic authored
llvm-svn: 202518
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Rafael Espindola authored
llvm-svn: 202510
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Sasa Stankovic authored
* Align targets of indirect jumps to instruction bundle boundaries (in MI layer). * Add masking instructions before indirect jumps (in MC layer). Differential Revision: http://llvm-reviews.chandlerc.com/D2847 llvm-svn: 202479
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Hal Finkel authored
The PPC isel instruction can fold 0 into the first operand (thus eliminating the need to materialize a zero-containing register when the 'true' result of the isel is 0). When the isel is fed by a bit register operation that we can invert, do so as part of the bit-register-operation peephole routine. llvm-svn: 202469
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Rafael Espindola authored
A really simple patch marks the end of a lot of yak shaving :-) llvm-svn: 202463
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Hal Finkel authored
This change enables tracking i1 values in the PowerPC backend using the condition register bits. These bits can be treated on PowerPC as separate registers; individual bit operations (and, or, xor, etc.) are supported. Tracking booleans in CR bits has several advantages: - Reduction in register pressure (because we no longer need GPRs to store boolean values). - Logical operations on booleans can be handled more efficiently; we used to have to move all results from comparisons into GPRs, perform promoted logical operations in GPRs, and then move the result back into condition register bits to be used by conditional branches. This can be very inefficient, because the throughput of these CR <-> GPR moves have high latency and low throughput (especially when other associated instructions are accounted for). - On the POWER7 and similar cores, we can increase total throughput by using the CR bits. CR bit operations have a dedicated functional unit. Most of this is more-or-less mechanical: Adjustments were needed in the calling-convention code, support was added for spilling/restoring individual condition-register bits, and conditional branch instruction definitions taking specific CR bits were added (plus patterns and code for generating bit-level operations). This is enabled by default when running at -O2 and higher. For -O0 and -O1, where the ability to debug is more important, this feature is disabled by default. Individual CR bits do not have assigned DWARF register numbers, and storing values in CR bits makes them invisible to the debugger. It is critical, however, that we don't move i1 values that have been promoted to larger values (such as those passed as function arguments) into bit registers only to quickly turn around and move the values back into GPRs (such as happens when values are returned by functions). A pair of target-specific DAG combines are added to remove the trunc/extends in: trunc(binary-ops(binary-ops(zext(x), zext(y)), ...) and: zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...) In short, we only want to use CR bits where some of the i1 values come from comparisons or are used by conditional branches or selects. To put it another way, if we can do the entire i1 computation in GPRs, then we probably should (on the POWER7, the GPR-operation throughput is higher, and for all cores, the CR <-> GPR moves are expensive). POWER7 test-suite performance results (from 10 runs in each configuration): SingleSource/Benchmarks/Misc/mandel-2: 35% speedup MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown MultiSource/Applications/lemon/lemon: 8% slowdown llvm-svn: 202451
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- Feb 27, 2014
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Roman Divacky authored
expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. llvm-svn: 202422
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Adrian Prantl authored
scan the register file for sub- and super-registers. No functionality change intended. (Tests are updated because the comments in the assembler output are different.) llvm-svn: 202416
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Richard Osborne authored
If a function returns a large struct by value return the first 4 words in registers and the rest on the stack in a location reserved by the caller. This is needed to support the xC language which supports functions returning an arbitrary number of return values. This is r202397 reapplied with a fix to avoid an uninitialized read of a member. llvm-svn: 202414
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Richard Osborne authored
These are causing test failures, revert for now. llvm-svn: 202398
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Richard Osborne authored
Summary: If a function returns a large struct by value return the first 4 words in registers and the rest on the stack in a location reserved by the caller. This is needed to support the xC language which supports functions returning an arbitrary number of return values. Reviewers: robertlytton Reviewed By: robertlytton CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2889 llvm-svn: 202397
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Richard Osborne authored
Summary: If the src, dst and size of a memcpy are known to be 4 byte aligned we can call __memcpy_4() instead of memcpy(). Reviewers: robertlytton Reviewed By: robertlytton CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2871 llvm-svn: 202395
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Richard Osborne authored
These instructions ignore the high bits of one of their input operands - try and use this to simplify the code. llvm-svn: 202394
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Richard Osborne authored
llvm-svn: 202393
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Daniel Sanders authored
Summary: Fixes an issue where a test attempts to use -mcpu=x86-64 on non-X86-64 targets. This triggers an assertion in the MIPS backend since it doesn't know what ABI to use by default for unrecognized processors. CC: llvm-commits, rafael Differential Revision: http://llvm-reviews.chandlerc.com/D2877 llvm-svn: 202369
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Eric Christopher authored
any ranges - this includes CU ranges where we were previously emitting an end list marker even if we didn't have a list. Testcase includes a test for line table only code emission as the problem was noticed while writing this test. llvm-svn: 202357
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Juergen Ributzka authored
This reverts commit r202283, because when we use GuardMalloc the test will fail due to additional output to std err. llvm-svn: 202341
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Michel Danzer authored
If the SI_KILL operand is constant, we can either clear the exec mask if the operand is negative, or do nothing otherwise. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 202337
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Michel Danzer authored
Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 202336
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Eric Christopher authored
any ranges to the list of ranges for the CU as we don't want to emit them anyway. This ensures that we will still emit ranges if we have a compile unit compiled with only line tables and one compiled with full debug info requested (we'll emit for the one with full debug info). Update testcase metadata accordingly to continue emitting ranges. llvm-svn: 202333
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