Commits · 2312a3aaa00c276359ab8f474012ecf4f2007a08 · Roger Ferrer / llvm-epi-0.8

Oct 18, 2011

Final patch that completes old JIT support for Mips: · 2312a3aa

Bruno Cardoso Lopes authored Oct 18, 2011

-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378

2312a3aa

Coding style cleanups. No functionality change. · 2b7a1ff7
Bill Wendling authored Oct 18, 2011
```
llvm-svn: 142341
```
2b7a1ff7
Fix misc warnings. Patch by Joe Abbey. · 4c42be5b
Eli Friedman authored Oct 18, 2011
```
llvm-svn: 142332
```
4c42be5b

Oct 17, 2011
- Add definitions of conditional moves with 64-bit operands. Comment out code for · a7e0b908
  Akira Hatanaka authored Oct 17, 2011
```
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
```
  a7e0b908
- Move class and instruction definitions for conditional moves to a seperate file. · 975bfc9b
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142220
```
  975bfc9b
- Revert change made in r142205. · 3634f346
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142217
```
  3634f346
- Redefine count-leading 0s and 1s instructions. · 33fe8f90
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142216
```
  33fe8f90
- Redefine mfhi/lo and mthi/lo instructions. · 8c446be2
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142214
```
  8c446be2
- Redefine multiply and divide instructions. · 0317b653
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142211
```
  0317b653
- Add definition of a base class for logical shift/rotate instructions with two · 2736bbc0
  Akira Hatanaka authored Oct 17, 2011
```
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
```
  2736bbc0
- Add definition of a base class for logical shift/rotate immediate instructions · 73081309
  Akira Hatanaka authored Oct 17, 2011
```
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
```
  73081309
- Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. · e3f27b79
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142205
```
  e3f27b79
Oct 14, 2011
- Add f128 to datalayout string. · 44419bfd
  Akira Hatanaka authored Oct 14, 2011
```
llvm-svn: 141978
```
  44419bfd
- Revert r141932, r141936 and r141937. · 62b34a65
  Akira Hatanaka authored Oct 14, 2011
```
llvm-svn: 141959
```
  62b34a65
- Definition of function getMipsRegisterNumbering. · d9ea7c8c
  Akira Hatanaka authored Oct 14, 2011
```
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141938
```
  d9ea7c8c
- Add definition of class MipsELFWriterInfo. · 1742a2c0
  Akira Hatanaka authored Oct 14, 2011
```
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141937
```
  1742a2c0
- Add missing relocation types. · 0fc7d7af
  Akira Hatanaka authored Oct 14, 2011
```
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141936
```
  0fc7d7af
- Fixup enumerations. · 769fc971
  Akira Hatanaka authored Oct 14, 2011
```
Patch by Jack Carter at Mips. 

llvm-svn: 141934
```
  769fc971
- Add more Mips relocation types. · 4e2bfe07
  Akira Hatanaka authored Oct 14, 2011
```
Patch by Jack Carter at Mips. 

llvm-svn: 141932
```
  4e2bfe07
Oct 12, 2011
- Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. · 3261c0fa
  Akira Hatanaka authored Oct 12, 2011
```
llvm-svn: 141761
```
  3261c0fa
- Fix encoding of 32-bit integer instructions. Change names of operands and nodes. · c57febff
  Akira Hatanaka authored Oct 12, 2011
```
Remove unused classes.

llvm-svn: 141757
```
  c57febff
- Change name of class to ArithOverflowR. · 0f4ecf75
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141743
```
  0f4ecf75
- Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical · 8f0d549c
  Akira Hatanaka authored Oct 11, 2011
```
instructions with two register operands derive from it.

llvm-svn: 141742
```
  8f0d549c
- Fix comment. · 8d4f74a6
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141737
```
  8d4f74a6
- Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit · ae5a9d65
  Akira Hatanaka authored Oct 11, 2011
```
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
```
  ae5a9d65
- Fix function isUnalignedLoadStore. · 1c184658
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141722
```
  1c184658
Oct 11, 2011
- Remove unused PatLeaf. · 10ae11fd
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141720
```
  10ae11fd
- Change the names of 64-bit logical instructions so that they match the names of · 453ac88b
  Akira Hatanaka authored Oct 11, 2011
```
the real instructions.

llvm-svn: 141718
```
  453ac88b
- Remove redundancy in setcc patterns using multiclass. · 46a7994a
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141715
```
  46a7994a
- Use sltiu instead of sltu when a register operand and immediate are compared. · 8c1c5104
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141708
```
  8c1c5104
- Add patterns for conditional branches with 64-bit register operands. · 7148bce8
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141696
```
  7148bce8
- Add support for 64-bit set-on-less-than instructions. · f75add62
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141695
```
  f75add62
- Add support for conditional branch instructions with 64-bit register operands. · 4b6ac98f
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141694
```
  4b6ac98f
- Make changes necessary for supporting floating point load and store instructions · b6d72cbe
  Akira Hatanaka authored Oct 11, 2011
```
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
```
  b6d72cbe
- Modify lowering of GlobalAddress so that correct code is emitted when target is · 09b23eb7
  Akira Hatanaka authored Oct 11, 2011
```
Mips64.

llvm-svn: 141618
```
  09b23eb7
- Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. · fa55bc27
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141615
```
  fa55bc27
- Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. · e6ced5b3
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141613
```
  e6ced5b3
- Add definitions of 64-bit loads and stores. Add a patterns for unaligned · be68f3c3
  Akira Hatanaka authored Oct 11, 2011
```
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
```
  be68f3c3
- Change definitions of classes LoadM and StoreM in preparation for adding support · fd2d7dcc
  Akira Hatanaka authored Oct 11, 2011
```
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
```
  fd2d7dcc
Oct 08, 2011
- Simplify definition of FP move instructions. · 6be7d6c9
  Akira Hatanaka authored Oct 08, 2011
```
llvm-svn: 141476
```
  6be7d6c9