- Jan 10, 2012
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Benjamin Kramer authored
llvm-svn: 147874
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Richard Smith authored
llvm-svn: 147870
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Bill Wendling authored
As the comment around 7746 says, it's better to use the x87 extended precision here than SSE. And the generic code doesn't know how to do that. It also regains the speed lost for the uint64_to_float.c testcase. <rdar://problem/10669858> llvm-svn: 147869
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Richard Smith authored
llvm-svn: 147867
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Chandler Carruth authored
of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
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Devang Patel authored
Right now, this just adds additional entries in match table. The parser does not use them yet. llvm-svn: 147859
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David Blaikie authored
llvm-svn: 147855
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Benjamin Kramer authored
llvm-svn: 147846
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Craig Topper authored
Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside. llvm-svn: 147844
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Craig Topper authored
Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is the final piece to remove the AVX hack that disabled SSE. llvm-svn: 147843
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Craig Topper authored
Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. AVX is now an SSE level and no longer disables SSE checks. llvm-svn: 147842
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Craig Topper authored
Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget. llvm-svn: 147841
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Jakob Stoklund Olesen authored
On Thumb, the displacement computation hardware uses the address of the current instruction rouned down to a multiple of 4. Include this rounding in the UserOffset we compute for each instruction. When inline asm is present, the instruction alignment may not be known. Constrain the maximum displacement instead in that case. This makes it possible for CreateNewWater() and OffsetIsInRange() to agree about the valid displacements. When they disagree, infinite looping happens. As always, test cases for this stuff are insane. <rdar://problem/10660175> llvm-svn: 147825
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Rafael Espindola authored
llvm-svn: 147820
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- Jan 09, 2012
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Jakob Stoklund Olesen authored
The pass is prone to looping, and it is better to crash than loop forever, even in a -Asserts build. <rdar://problem/10660175> llvm-svn: 147806
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Devang Patel authored
llvm-svn: 147805
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Devang Patel authored
AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. llvm-svn: 147787
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Chandler Carruth authored
this substraction will result in small negative numbers at worst which become very large positive numbers on assignment and are thus caught by the <=4 check on the next line. The >0 check clearly intended to catch these as negative numbers. Spotted by inspection, and impossible to trigger given the shift widths that can be used. llvm-svn: 147773
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Craig Topper authored
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior. llvm-svn: 147770
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Craig Topper authored
llvm-svn: 147769
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Craig Topper authored
Reorder a bunch of patterns to put the AVX version first thus giving it priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget. llvm-svn: 147768
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Craig Topper authored
Clean up patterns for MOVNT*. Not sure why there were floating point types on MOVNTPS and MOVNTDQ. And v4i64 was completely missing. llvm-svn: 147767
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Craig Topper authored
Mark MOVNTI as being supported in SSE2 OR AVX mode. This instruction has no AVX equivalent so we should use the SSE version. llvm-svn: 147766
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Craig Topper authored
Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues. llvm-svn: 147765
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Craig Topper authored
Change some places that were checking for AVX OR SSE1/2 to use hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h llvm-svn: 147764
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Craig Topper authored
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level. llvm-svn: 147762
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Craig Topper authored
llvm-svn: 147758
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- Jan 08, 2012
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Evan Cheng authored
llvm-svn: 147752
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Victor Umansky authored
llvm-svn: 147748
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- Jan 07, 2012
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Jakob Stoklund Olesen authored
Darwin doesn't do static, and ELF targets only support static. llvm-svn: 147740
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Craig Topper authored
llvm-svn: 147739
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Benjamin Kramer authored
llvm-svn: 147738
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Craig Topper authored
llvm-svn: 147734
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Jakob Stoklund Olesen authored
This enables basic local CSE, giving us 20% smaller code for consumer-typeset in -O0 builds. <rdar://problem/10658692> llvm-svn: 147720
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Rafael Espindola authored
file error checking. Use that to error on an unfinished cfi_startproc. The error is not nice, but is already better than a segmentation fault. llvm-svn: 147717
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Evan Cheng authored
exposed with an upcoming change will would delete the copy to return register because there is no use! It's amazing anything works. llvm-svn: 147715
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Jakob Stoklund Olesen authored
This eliminates a lot of constant pool entries for -O0 builds of code with many global variable accesses. This speeds up -O0 codegen of consumer-typeset by 2x because the constant island pass no longer has to look at thousands of constant pool entries. <rdar://problem/10629774> llvm-svn: 147712
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Eric Christopher authored
Fixes rdar://10614894 llvm-svn: 147704
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- Jan 06, 2012
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Jakob Stoklund Olesen authored
Experiments show this to be a small speedup for modern ARM cores. llvm-svn: 147689
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Jakob Stoklund Olesen authored
llvm-svn: 147685
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