Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.

llvm-svn: 141274

llvm-svn: 141266

This restores my karma after I added TRI::getSubClassWithSubReg().

Register constraints are applied 'backwards'.  Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.

We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in?  The
getSubRegisterRegClass() hook did that.

llvm-svn: 141258

Add vim highlighting support for multidefs.

llvm-svn: 141238

Add Emacs font-lock keyword support for multidefs.

llvm-svn: 141237

This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

llvm-svn: 141142

This should unbreak the Windows build.

llvm-svn: 141105

The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference:  For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0.  This class was omitted from the .td
file on purpose because it only has two registers.  InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8.  I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

  GR64_with_sub_8bit
  GR64_TC_with_sub_8bit
  GR64_NOREX_with_sub_8bit
  GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

llvm-svn: 141084

There is no need to keep the primary order separate.

llvm-svn: 141082

When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference.  All register classes must have a
name, though.

llvm-svn: 141081

The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.

llvm-svn: 141080

Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.

llvm-svn: 141065

llvm-svn: 141057

llvm-svn: 141013

llvm-svn: 140962

llvm-svn: 140955

Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.

llvm-svn: 140954

This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951

llvm-svn: 140928

All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905

This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898

This one can also print 32-bit groups.

llvm-svn: 140897

Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895

Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

llvm-svn: 140882

llvm-svn: 140827

All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826

This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816

"show-in-system-header" bits, which I will be adding in Clang shortly.

llvm-svn: 140741

llvm-svn: 140573

llvm-svn: 140560

Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

llvm-svn: 140472

llvm-svn: 140370

No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160

Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134

llvm-svn: 140121

llvm-svn: 140078

Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.

llvm-svn: 140034

llvm-svn: 139936

this anymore.

llvm-svn: 139935

Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.

llvm-svn: 139691