llvm-svn: 188017

No functionality change.

llvm-svn: 188016

llvm-svn: 187863

llvm-svn: 187838

llvm-svn: 187832

instructions defined in MipsInstrInfo.td as codegen-only instructions.

llvm-svn: 187828

EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.

llvm-svn: 187824

unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821

Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.

Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

llvm-svn: 187780

helper functions. This can be optimized out later when the remaining
parts of the helper function work is moved into the Mips16HardFloat pass.
For now it forces us to use the 32 bit save/restore instructions instead
of the 16 bit ones.

llvm-svn: 187712

llvm-svn: 187701

llvm-svn: 187695

llvm-svn: 187667

remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.

llvm-svn: 187632

This is actually an LLVM bug in the way it generates signatures for these
when soft float is enabled. For example, floor ends up having the signature
of int64(int64). The signature part is not the same as where the actual
parameter types are recorded, and those ARE of course int64(int64) when
soft float is enabled. (Yes, Mips16 hard float uses soft float but with
different runtime rounes but then has to interoperate with Mips32 using
normal floating point). This logic will eventually be moved to the 
Mips16HardFloat pass so it's not worth sorting out these issues in LLVM
since nobody but Mips16 cares about these signatures, as far as I know,
and even I won't eventually either.

llvm-svn: 187613

Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.

llvm-svn: 187569

1) They should never be inlined.
2) A naming inconsistency with gcc mips16
3) Stubs should not have the global attribute

llvm-svn: 187555

llvm-svn: 187553

No functionality change.

llvm-svn: 187469

No functionality change.

llvm-svn: 187468

llvm-svn: 187443

turns "bal" into "bgezal".

llvm-svn: 187440

This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.

llvm-svn: 187410

llvm-svn: 187371

Patch by Sasa Stankovic.

llvm-svn: 187244

register operands.

llvm-svn: 187242

operands.

llvm-svn: 187238

llvm-svn: 187234

to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.

llvm-svn: 187233

needed. The generic method printOperand will do.

No functionality change.

llvm-svn: 187231

instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3

llvm-svn: 187229

when there wasn't a match. This behavior is consistent with other register
parsing methods.

llvm-svn: 187063

Testing commit access credentials.

llvm-svn: 187032

This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.

llvm-svn: 187026

Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861

the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855

No functionality change.

llvm-svn: 186642

This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.

llvm-svn: 186567

llvm-svn: 186528

This patch checks for valid mnemonics at the beginning of parseInstruction method, thus giving the user the right error message for non-existing instructions.

llvm-svn: 186512