the LowerPartSet(). It didn't handle the situation correctly when
the low, high argument values are in reverse order (low > high)
with 'Val' type i32 (a corner case).

llvm-svn: 63388

Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.

llvm-svn: 63377

llvm-svn: 63376

llvm-svn: 63375

llvm-svn: 63374

llvm-svn: 63373

llvm-svn: 63372

llvm-svn: 63371

If a MachineInstr doesn't have a memoperand but has an opcode that
is known to load or store, assume its memory reference may alias
*anything*, including stack slots which the compiler completely
controls.

To partially compensate for this, teach the ScheduleDAG building
code to do basic getUnderlyingValue analysis. This greatly
reduces the number of instructions that require restrictive
dependencies. This code will need to be revisited when we start
doing real alias analysis, but it should suffice for now.

llvm-svn: 63370

llvm-svn: 63369

llvm-svn: 63368

llvm-svn: 63367

llvm-svn: 63366

- Modify ReassociateOps so that the resulting SDValue is what the comment claims
  it is.

llvm-svn: 63365

llvm-svn: 63359

llvm-svn: 63358

llvm-svn: 63357

llvm-svn: 63356

llvm-svn: 63355

llvm-svn: 63350

Correct the algorithms for choosing spill and restore points so that we don't try to insert loads/stores between call frame setup and the actual call.

This fixes the last known failure for the pre-alloc-splitter.

llvm-svn: 63339

BUILD_VECTOR and conversions to stack operations.

llvm-svn: 63333

some assertions.

llvm-svn: 63328

Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins.

llvm-svn: 63323

llvm-svn: 63312

the element indices may be equal if either one is not a
constant.

llvm-svn: 63311

change.

llvm-svn: 63301

and an iterator invalidation issue.

FreeBench/pifft no longer miscompiles with these fixes!

llvm-svn: 63293

llvm-svn: 63276

vast majority of code size regressions introduced by pre-alloc-splitting.

llvm-svn: 63274

- Modify TableGen to add the DebugLoc when calling getTargetNode.

(The light-weight wrappers are only temporary. The non-DebugLoc version will be
removed once the whole debug info stuff is finished with.)

llvm-svn: 63273

llvm-svn: 63267

dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266

A slight compile time optimization. If the caller knows there isn't a free register getReg() should not call getFreeReg().

llvm-svn: 63263

functions.  Currently omitted:  memcpy, memmove, memset.

llvm-svn: 63259

llvm-svn: 63255

llvm-svn: 63245

classes (those that reasonably have a DebugLoc
associated with them).

llvm-svn: 63236

Do not forget to derived type while constructing an array type.

llvm-svn: 63233

llvm-svn: 63217