changes before doing phi lowering for switches.

llvm-svn: 102809

indexes could be of a different value type. Or not even using the same SDNode
for the constant (weird, I know). Compare the actual values instead of the
pointers.

llvm-svn: 102791

instruction selection is done; it's confusing to see parts of it printed,
while other parts are omitted, along the way.

llvm-svn: 102771

call that might throw. The landing pad assumes that all registers are in stack
slots.

We used to spill those dirty CSRs after the call, and the stack slots would be
wrong when arriving at the landing pad.

llvm-svn: 102770

llvm-svn: 102743

llvm-svn: 102742

Rounding differences causes tests to fail on Linux.

llvm-svn: 102729

comparisons sign-extended to a different bitwidth than the
comparison operands.

llvm-svn: 102721

llvm-svn: 102680

easy cases.

llvm-svn: 102678

of different register classes. e.g.

  %reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3

Where %reg1048 is a GR32 register. This is not impossible to handle, but it is
pretty hard and very rare.

This should unbreak the dragonegg builder.

llvm-svn: 102672

llvm-svn: 102666

llvm-svn: 102663

llvm-svn: 102661

llvm-svn: 102657

	##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
	##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
	##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
	##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
	##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0

llvm-svn: 102655

llvm-svn: 102654

llvm-svn: 102653

llvm-svn: 102606

llvm-svn: 102602

llvm-svn: 102590

llvm-svn: 102585

llvm-svn: 102584

llvm-svn: 102581

llvm-svn: 102573

- Also, update dbg_value is the value is being re-matted from a frame slot, e.g. fixed slots for arguments.

llvm-svn: 102565

llvm-svn: 102558

Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.

llvm-svn: 102554

Before:
DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707
Now:
DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707

llvm-svn: 102518

alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).

llvm-svn: 102515

While lowering dbg_declare, emit DBG_VALUE machine instruction if alloca matching llvm.dbg.declare intrinsic is missing.

llvm-svn: 102513

update them. Computing kill flags is notoriously difficult, and the coalescer
would get it wrong sometimes, and it would completely skip physical registers.

Now we simply remove kill flags based on the live intervals after coalescing.
This is a few percent slower, but now we get correct kill flags for physical
registers after coalescing.

llvm-svn: 102510

llvm-svn: 102492

llvm-svn: 102486

ForcedAlignBits argument, tweaking the single client of it.

llvm-svn: 102484

llvm-svn: 102483

llvm-svn: 102482

llvm-svn: 102481

llvm-svn: 102470

llvm-svn: 102468