- Apr 01, 2011
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Owen Anderson authored
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately. llvm-svn: 128739
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Jim Grosbach authored
llvm-svn: 128736
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Johnny Chen authored
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction as invalid. llvm-svn: 128734
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Akira Hatanaka authored
Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly. llvm-svn: 128724
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Johnny Chen authored
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722
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Akira Hatanaka authored
llvm-svn: 128718
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Benjamin Kramer authored
llvm-svn: 128709
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Evan Cheng authored
rdar://8911343 llvm-svn: 128696
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Matt Beaumont-Gay authored
llvm-svn: 128692
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Bruno Cardoso Lopes authored
all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
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Jakob Stoklund Olesen authored
The LocalStackSlotAllocation pass was creating illegal registers. llvm-svn: 128687
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- Mar 31, 2011
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Evan Cheng authored
accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 llvm-svn: 128665
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Johnny Chen authored
Inst{4} = 0. rdar://problem/9213022 llvm-svn: 128662
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Akira Hatanaka authored
llvm-svn: 128650
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Johnny Chen authored
A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644
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Bruno Cardoso Lopes authored
llvm-svn: 128635
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Richard Osborne authored
llvm-svn: 128633
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Bruno Cardoso Lopes authored
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
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Matt Beaumont-Gay authored
This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
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Owen Anderson authored
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. llvm-svn: 128587
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Evan Cheng authored
llvm-svn: 128586
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Bruno Cardoso Lopes authored
{STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
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Cameron Zwarich authored
can be recognized. This fixes <rdar://problem/9183078>. llvm-svn: 128584
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- Mar 30, 2011
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Akira Hatanaka authored
llvm-svn: 128574
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Jay Foad authored
PHINode::Create() giving the (known or expected) number of operands. llvm-svn: 128537
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Evan Cheng authored
was lowering them to sext / uxt + mul instructions. Unfortunately the optimization passes may hoist the extensions out of the loop and separate them. When that happens, the long multiplication instructions can be broken into several scalar instructions, causing significant performance issue. Note the vmla and vmls intrinsics are not added back. Frontend will codegen them as intrinsics vmull* + add / sub. Also note the isel optimizations for catching mul + sext / zext are not changed either. First part of rdar://8832507, rdar://9203134 llvm-svn: 128502
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- Mar 29, 2011
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Cameron Zwarich authored
<rdar://problem/8875309> and <rdar://problem/9057191>. llvm-svn: 128492
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Owen Anderson authored
Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases. llvm-svn: 128481
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Johnny Chen authored
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 llvm-svn: 128478
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Owen Anderson authored
llvm-svn: 128467
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Owen Anderson authored
llvm-svn: 128461
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Evan Cheng authored
Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during isel lowering to fold the zero-extend's and take advantage of no-stall back to back vmul + vmla: vmull q0, d4, d6 vmlal q0, d5, d6 is faster than vaddl q0, d4, d5 vmovl q1, d6 vmul q0, q0, q1 This allows us to vmull + vmlal for: f = vmull_u8( vget_high_u8(s), c); f = vmlal_u8(f, vget_low_u8(s), c); rdar://9197392 llvm-svn: 128444
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Daniel Dunbar authored
integrated-as. llvm-svn: 128431
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- Mar 28, 2011
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Johnny Chen authored
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. llvm-svn: 128417
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Che-Liang Chiou authored
llvm-svn: 128405
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- Mar 26, 2011
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Benjamin Kramer authored
llvm-svn: 128338
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Johnny Chen authored
llvm-svn: 128322
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Eric Christopher authored
masks to match inversely for the code as is to work. For the example given we actually want: bfi r0, r2, #1, #1 not #0, however, given the way the pattern is written it's not possible at the moment. Fixes rdar://9177502 llvm-svn: 128320
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- Mar 25, 2011
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Johnny Chen authored
Also add some test cases. rdar://problem/9189829 llvm-svn: 128304
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Johnny Chen authored
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. rdar://problem/9182892 llvm-svn: 128299
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