- Jul 04, 2013
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Eric Christopher authored
for them and update all uses. llvm-svn: 185588
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- Jul 03, 2013
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Quentin Colombet authored
In the ARM back-end, build_vector nodes are lowered to a target specific build_vector that uses floating point type. This works well, unless the inserted bitcasts survive until instruction selection. In that case, they incur moves between integer unit and floating point unit that may result in inefficient code. In other words, this conversion may introduce artificial dependencies when the code leading to the build vector cannot be completed with a floating point type. In particular, this happens when loads are not aligned. Before this patch, in that case, the compiler generates general purpose loads and creates the floating point vector from them, instead of directly using the vector unit. The patch uses a vector friendly sequence of code when the inserted bitcasts to floating point survived DAGCombine. This is done by a target specific DAGCombine that changes the target specific build_vector into a sequence of insert_vector_elt that get rid of the bitcasts. <rdar://problem/14170854> llvm-svn: 185587
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Eric Christopher authored
llvm-svn: 185586
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Eric Christopher authored
(and for consistency). llvm-svn: 185585
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Bill Schmidt authored
Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous. llvm-svn: 185583
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Renato Golin authored
llvm-svn: 185581
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Tilmann Scheller authored
ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings. Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. llvm-svn: 185575
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Eric Christopher authored
llvm-svn: 185573
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Chad Rosier authored
Patch by Alex Crichton <alex@crichton.co>. Approved by Chris Lattner. llvm-svn: 185566
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Ulrich Weigand authored
[PowerPC] Support lmw/stmw in the asm parser This adds support for the load/store multiple instructions, currently used by the asm parser only. llvm-svn: 185564
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Ulrich Weigand authored
[PowerPC] Use mtocrf when available Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. llvm-svn: 185561
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Ulrich Weigand authored
[PowerPC] Always use mfocrf if available When accessing just a single CR register, it is always preferable to use mfocrf instead of mfcr, if the former is available on the CPU. Current code makes that distinction in many, but not all places where a single CR register value is retrieved. One missing location is PPCRegisterInfo::lowerCRSpilling. To fix this and make this simpler in the future, this patch changes the bulk of the back-end to always assume mfocrf is available and simply generate it when needed. On machines that actually do not support mfocrf, the instruction is replaced by mfcr at the very end, in EmitInstruction. This has the additional benefit that we no longer need the MFCRpseud hack, since before EmitInstruction we always have a MFOCRF instruction pattern, which already models data flow as required. The patch also adds the MFOCRF8 version of the instruction, which was missing so far. Except for the PPCRegisterInfo::lowerCRSpilling case, no change in generated code intended. llvm-svn: 185556
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Rafael Espindola authored
llvm-svn: 185554
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Rafael Espindola authored
It was only passing because 'grep andpd' was not finding any andpd, but we don't fail if part of a pipe fails. llvm-svn: 185552
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Rafael Espindola authored
llvm-svn: 185551
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Rafael Espindola authored
llvm-svn: 185550
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Rafael Espindola authored
While there, use early returns to reduce nesting. llvm-svn: 185547
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Rafael Espindola authored
This is a small compatibility improvement with gnu nm and makes llvm-nm more useful as a testing tool. llvm-svn: 185546
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Ulrich Weigand authored
[PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCC The subroutine getCRIdxForSetCC has a parameter "Other" and comment: If this returns with Other != -1, then the returned comparison is an or of two simpler comparisons. However for at least the last five years this routine has never returned a value of Other != -1; these cases are now handled differently to begin with. This patch removes the parameter and the code in SelectSETCC that attempted to handle the Other != -1 case. llvm-svn: 185541
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Craig Topper authored
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. llvm-svn: 185540
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Craig Topper authored
Fix regular expression used by 'make update' to only look for 'I' and '?' at the start of svn info results and to check for spaces after 'I' instead of just after '?'. Previously it was able to match 'I' anywhere in the filenames of the svn info results instead of just files that where ignored or unknown to svn. This would cause 'make update' to infinitely recurse if a file was modified with I anywhere in its name since svn info would return a Path pointing to the llvm root for those files. llvm-svn: 185539
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Evgeniy Stepanov authored
This changes behavior of -msan-poison-stack=0 flag from not poisoning stack allocations to actively unpoisoning them. llvm-svn: 185538
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Ulrich Weigand authored
[PowerPC] Make specialized AltiVec patterns isCodeGenOnly A couple of AltiVec patterns are just specialized forms of the generic instruction pattern, and should therefore be marked isCodeGenOnly to avoid confusing the asm parser: VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES. Noticed by inspection of the generated PPCGenAsmMatcher.inc. llvm-svn: 185533
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Ulrich Weigand authored
[PowerPC] Support mtspr/mfspr in the asm parser This adds support for the generic forms of mtspr/mfspr for the asm parser. The compiler will continue to use the specialized patters for mtlr etc. since those are needed to correctly describe data flow. llvm-svn: 185532
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Richard Sandiford authored
Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). llvm-svn: 185529
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Mihai Popa authored
1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
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Tim Northover authored
Swift cores implement store barriers that are stronger than the ARM specification but weaker than general barriers. They are, in fact, just about enough to provide the ordering needed for atomic operations with release semantics. This patch makes use of that quirk. llvm-svn: 185527
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Richard Sandiford authored
Rename Function->DispKey and PairType->DispSize. I'd originally used "Function" because I thought it might be useful for other InstMappings. However, it turns out that having two very similar instructions with the same Function makes it pretty useless for anything other than the displacement size key. Other InstMappings will want the key to be defined for only one instruction in the pair. No behavioural change intended. llvm-svn: 185526
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Richard Sandiford authored
Get rid of some old code (and associated FIXME) for handling the caller-allocated register save area. No behavioural change intended. llvm-svn: 185525
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Eric Christopher authored
llvm-svn: 185523
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Eric Christopher authored
llvm-svn: 185520
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Richard Osborne authored
llvm-svn: 185519
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Richard Osborne authored
Patch by Robert Lytton. llvm-svn: 185518
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Craig Topper authored
llvm-svn: 185514
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Craig Topper authored
llvm-svn: 185513
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Craig Topper authored
Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily. llvm-svn: 185512
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Eric Christopher authored
to avoid specifying the vector size. llvm-svn: 185511
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Craig Topper authored
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. llvm-svn: 185509
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Craig Topper authored
Introduce some typedefs for DenseMaps containing SmallVectors so the vector size doesn't have to repeated when creating iterators for the DenseMap. llvm-svn: 185508
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Craig Topper authored
Return SmallVectorImpl& instead of SmallVector& in a couple places to avoid having to specify the vector size in multiple places. llvm-svn: 185507
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