Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.

e.g.
        vldr.32 s0, [r1]
        vldr.32 s1, [r0]
        vcmpe.f32       s1, s0
        vmrs    apsr_nzcv, fpscr
	beq     LBB0_2
=>
        ldr     r1, [r1]
        ldr     r0, [r0]
        cmp     r0, r1
        beq     LBB0_2

More complicated cases will be implemented in subsequent patches.

llvm-svn: 107852

Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851

llvm-svn: 107831

address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682

llvm-svn: 107830

llvm-svn: 107811

code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786

llvm-svn: 107743

they've been tested to work.

llvm-svn: 107742

than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

llvm-svn: 107734

allocated to consecutive registers.

llvm-svn: 107730

This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725

llvm-svn: 107710

llvm-svn: 107701

the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691

if profitable.

llvm-svn: 107673

llvm-svn: 107668

the pseudo instruction is not at the end of the block.

llvm-svn: 107655

Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.

llvm-svn: 107550

llvm-svn: 107513

that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.

llvm-svn: 107487

getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer.  The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.

llvm-svn: 107435

llvm-svn: 107201

The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

llvm-svn: 107167

llvm-svn: 107154

a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.

llvm-svn: 107147

of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

llvm-svn: 107140

llvm-svn: 107135

and thumb_mode.

llvm-svn: 107133

llvm-svn: 107131

llvm-svn: 107127

llvm-svn: 107122

llvm-svn: 107121

llvm-svn: 107114

the same as ARM except that the condition code field is always set to ARMCC::AL.

llvm-svn: 107107

of the Subtarget.

llvm-svn: 107086

llvm-svn: 107073

llvm-svn: 107070

llvm-svn: 107068

llvm-svn: 106988

llvm-svn: 106940