*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906

various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884

Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862

and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861

got a dulicated line).

llvm-svn: 117860

llvm-svn: 117859

Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858

llvm-svn: 117848

llvm-svn: 117787

llvm-svn: 117782

llvm-svn: 117771

llvm-svn: 117769

llvm-svn: 117766

There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756

llvm-svn: 117753

conditional. Check for those instructions explicitly.

llvm-svn: 117747

llvm-svn: 117742

llvm-svn: 117741

llvm-svn: 117740

encoder functions.

llvm-svn: 117738

llvm-svn: 117737

llvm-svn: 117718

the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714

failure for llvm-gcc on arm fast isel.

llvm-svn: 117710

handle it in the asm lowering.

llvm-svn: 117707

llvm-svn: 117703

llvm-svn: 117702

llvm-svn: 117695

llvm-svn: 117687

operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.

llvm-svn: 117675

- Compute CopyToReg use operand latency correctly.

llvm-svn: 117674

llvm-svn: 117672

Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.

llvm-svn: 117667

llvm-svn: 117663

llvm-svn: 117660

llvm-svn: 117651

llvm-svn: 117648

fully enumerated.

llvm-svn: 117647

vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626

t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^

llvm-svn: 117611