should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688

want them later (mips32/64).

llvm-svn: 43380

- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.

llvm-svn: 43153

llvm-svn: 43150

llvm-svn: 42960

function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908

llvm-svn: 42780

- Added a function to hold the stack location 
  where GP must be stored during LowerCALL
- AsmPrinter now emits directives based on
  relocation type
- PIC_ set to default relocation type (same as GCC)

llvm-svn: 42779

- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.

llvm-svn: 42778

address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621

Tested with "make check"!

llvm-svn: 42346

llvm-svn: 42316

Fixed some comments

llvm-svn: 42271

llvm-svn: 41863

init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841

Patch by Sterling Stein!

llvm-svn: 41758

Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.

llvm-svn: 41597

Changed the stack frame layout, StackGrowsUp fits better to Mips strange stack.
Stack offset calculation bug fixed!

llvm-svn: 41529

Added comments about new stack allocation.
Expand SelectCC for i32 results

llvm-svn: 41527

Comments for Mips directives added.

llvm-svn: 41526

llvm-svn: 41525

llvm-svn: 41225

llvm-svn: 41224

MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions

llvm-svn: 41161

llvm-svn: 41160

llvm-svn: 41159

fixed to generate instructions (add, lui) glued!

llvm-svn: 41158

Newline added after macros at function init on generated asm!

llvm-svn: 41157

llvm-svn: 41156

llvm-svn: 41155

llvm-svn: 41154

Added InsertNoop support

llvm-svn: 41153

MipsAdd opcode added

llvm-svn: 41152

Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151

llvm-svn: 41150

llvm-svn: 41149

llvm-svn: 40757

still under discussion.

llvm-svn: 40549

AsmPrinter::doFinalization.

llvm-svn: 40487

llvm-svn: 40132