llvm-svn: 58789

llvm-svn: 58780

Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.

llvm-svn: 58764

changes.

llvm-svn: 58760

llvm-svn: 58755

llvm-svn: 58752

llvm-svn: 58750

priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748

by isel and potentially forced into registers.

llvm-svn: 58747

indirect gv reference. Please don't call it lazy.

llvm-svn: 58746

llvm-svn: 58725

llvm-svn: 58714

llvm-svn: 58708

llvm-svn: 58707

For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.

This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.

llvm-svn: 58688

llvm-svn: 58683

llvm-svn: 58671

have its node id set. The new and and shift nodes are the nodes that need
the IDs. This fixes PR2982.

llvm-svn: 58655

llvm-svn: 58644

llvm-svn: 58643

Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.

llvm-svn: 58626

adding a TargetMachine member to the base TargetAsmInfo class instead.

llvm-svn: 58624

llvm-svn: 58539

llvm-svn: 58533

llvm-svn: 58532

llvm-svn: 58529

llvm-svn: 58528

llvm-svn: 58527

llvm-svn: 58526

llvm-svn: 58523

Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm.

llvm-svn: 58517

callee-saved restore code. It could skip over conditional jumps
accidentally. Instead, just skip the "return" instructions.

llvm-svn: 58489

vector element 0 for a store, as it's smaller and faster.

llvm-svn: 58483

llvm-svn: 58474

(i32 for PPC, not i8).  Correct this, and some
formatting while there.

llvm-svn: 58451

getShiftAmountTy (i32 in the case of CellSPU).

llvm-svn: 58449

llvm-svn: 58433

One will only see an effect if legalizetype is not active.  Will move
support to LegalizeType soon.

llvm-svn: 58426

so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU.

N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is
still unexorcised code.

llvm-svn: 58415

llvm-svn: 58409