llvm-svn: 100815

api and update clients to use MCContext instead.

llvm-svn: 100808

I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.

llvm-svn: 100735

llvm-svn: 100714

llvm-svn: 100709

llvm-svn: 100697

llvm-svn: 100696

Next to work on is ARMDisassemblerCore.cpp.

llvm-svn: 100695

llvm-svn: 100693

ARMDecoderEmitter.cpp, with FIXME comment.

llvm-svn: 100690

a simple mapping of register names to IDs to
identify register tokens.

llvm-svn: 100685

DBG_VALUE does not generate code.

llvm-svn: 100681

It is not ready for public yet.

llvm-svn: 100673

llvm-svn: 100672

llvm-svn: 100671

llvm-svn: 100670

llvm-svn: 100669

llvm-svn: 100668

llvm-svn: 100667

llvm-svn: 100666

llvm-svn: 100665

llvm-svn: 100664

llvm-svn: 100663

llvm-svn: 100662

llvm-svn: 100661

llvm-svn: 100660

llvm-svn: 100659

llvm-svn: 100658

llvm-svn: 100657

llvm-svn: 100656

llvm-svn: 100655

llvm-svn: 100654

llvm-svn: 100653

VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.

llvm-svn: 100652

llvm-svn: 100651

Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(

llvm-svn: 100650

llvm-svn: 100649

llvm-svn: 100648

llvm-svn: 100647

Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.

llvm-svn: 100646