for SSE1, SSE2, SSE3, and SSSE3.

llvm-svn: 36656

llvm-svn: 36256

llvm-svn: 35869

llvm-svn: 35230

llvm-svn: 34905

llvm-svn: 34434

  or'ing in the sign bit of operand 1.
- Tweaking: rather than left shift the sign bit, fp_extend operand 1 first
  before taking its sign bit if its type is smaller than that of operand 0.

llvm-svn: 32932

llvm-svn: 32900

- Add MOVDI2SSrm and MOVSS2DImr to fold load / store for i32 <-> f32 bit_convert
  patterns.

llvm-svn: 32582

This compiles bitcast.ll:test3/test4 into:

_test3:
        movd %xmm0, %eax
        ret
_test4:
        movd %edi, %xmm0
        ret

llvm-svn: 32230

Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.

llvm-svn: 31795

take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.

This fixes PR996.

llvm-svn: 31645

shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.

Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>

llvm-svn: 31519

llvm-svn: 31435

llvm-svn: 31343

llvm-svn: 31228

llvm-svn: 31185

llvm-svn: 30892

folding first.

llvm-svn: 30848

llvm-svn: 30844

a framework for doing it right.  This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.

Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.

llvm-svn: 30817

llvm-svn: 30815

llvm-svn: 30814

llvm-svn: 30813

llvm-svn: 30812

llvm-svn: 30811

Fix a bug where the asmstring for PSUBQrm was wrong.

llvm-svn: 30810

llvm-svn: 30809

llvm-svn: 30808

  PDI_binop_rm -> PDI_binop_rm_int
  PDI_binop_rmi -> PDI_binop_rmi_int

to make it clear that these are for use with intrinsics.

llvm-svn: 30807

llvm-svn: 30806

llvm-svn: 30805

This allows us to use the multiclass for other packs.

llvm-svn: 30804

llvm-svn: 30800

llvm-svn: 30797

llvm-svn: 30796

llvm-svn: 30795

llvm-svn: 30794

llvm-svn: 30793

llvm-svn: 30792