llvm-svn: 37640

by making it non-recursive

llvm-svn: 37629

llvm-svn: 37626

llvm-svn: 37608

for tied register constraints.

llvm-svn: 37601

llvm-svn: 37597

llvm-svn: 37579

turned on.  Likewise for scanning of invokes to mark landing pads.

llvm-svn: 37570

VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.

This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.

llvm-svn: 37569

correct types for the result vector, even though it is currently bitcasted
to a different type immediately.

llvm-svn: 37568

crashing but breaks exception handling.  The problem
described in PR1224 is that invoke is a terminator that
can produce a value.  The value may be needed in other
blocks.  The code that writes to registers values needed
in other blocks runs before terminators are lowered (in
this case invoke) so asserted because the value was not
yet available.  The fix that was applied was to do invoke
lowering earlier, before writing values to registers.

The problem this causes is that the code to copy values
to registers can be output after the invoke call.  If
an exception is raised and control is passed to the
landing pad then this copy-code will never execute.  If
the value is needed in some code path reached via the
landing pad then that code will get something bogus.

So revert the original fix and simply skip invoke values
in the general copying to registers code.  Instead copy
the invoke value to a register in the invoke lowering code.

llvm-svn: 37567

llvm-svn: 37496

correct machine basic block - do not rely on the eh.exception intrinsic
being in the landing pad: the loop optimizers can move it out.

llvm-svn: 37463

llvm-svn: 37413

that the CSE map always contains explicit alignment information. This allows
more loads to be CSE'd when there is a mix of explicit-alignment loads and
implicit-alignment loads.

Also, in SelectionDAG::FindModifiedNodeSlot, add the operands to the
FoldingSetNodeID before the load/store information instead of after, so
that it matches what is done elsewhere.

llvm-svn: 37411

simplifies the code in DwarfWriter, allows for multiple filters and
makes it trivial to specify filters accompanied by cleanups or catch-all
specifications (see next patch).  What a deal!  Patch blessed by Anton.

llvm-svn: 37398

as a null i8 pointer not as a 0 i32.

llvm-svn: 37383

llvm-svn: 37362

llvm-svn: 37330

llvm-svn: 37321

llvm-svn: 37320

Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer.

llvm-svn: 37318

Mark all calls as "could throw", when exceptions are enabled. Emit necessary LP info too. This fixes PR1439

llvm-svn: 37311

llvm-svn: 37310

llvm-svn: 37249

this case, the xform introduces an extra operation).  This compiles
PowerPC/compare-duplicate.ll into:

_test:
        subf r2, r3, r4
        cmplw cr0, r2, r3
        bne cr0, LBB1_2 ;F

instead of:

_test:
        slwi r2, r3, 1
        subf r3, r3, r4
        cmplw cr0, r4, r2
        bne cr0, LBB1_2 ;F

This is target independent of course.

llvm-svn: 37246

llvm-svn: 37233

llvm-svn: 37230

i128 integers.  The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.

llvm-svn: 37169

add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets

llvm-svn: 37168

llvm-svn: 37134

llvm-svn: 37130

This fixes PR1423

llvm-svn: 37102

llvm-svn: 37094

llvm-svn: 37086

test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll

llvm-svn: 37069

CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr

llvm-svn: 37054

llvm-svn: 36962

Do not assert, when case range split metric is zero and JTs are not allowed: just emit binary tree in this case. This
fixes PR1403.

llvm-svn: 36959

llvm-svn: 36910