llvm-svn: 185586

(and for consistency).

llvm-svn: 185585

Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous.

llvm-svn: 185583

ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.

Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.

The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.

This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.

Fixes <rdar://problem/14224440>.

llvm-svn: 185575

llvm-svn: 185573

Patch by Alex Crichton <alex@crichton.co>.  Approved by Chris Lattner.

llvm-svn: 185566

[PowerPC] Support lmw/stmw in the asm parser

This adds support for the load/store multiple instructions,
currently used by the asm parser only.

llvm-svn: 185564

[PowerPC] Use mtocrf when available

Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.

Current code however always emits mtcrf.  This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible.  It does create
inefficient code with the integrated assembler, however.

To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything.  Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.

As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.

llvm-svn: 185561

[PowerPC] Always use mfocrf if available

When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.

Current code makes that distinction in many, but not all places
where a single CR register value is retrieved.  One missing
location is PPCRegisterInfo::lowerCRSpilling.

To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.

On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.

This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.

The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.

Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.

llvm-svn: 185556

While there, use early returns to reduce nesting.

llvm-svn: 185547

[PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCC

The subroutine getCRIdxForSetCC has a parameter "Other" and comment:

  If this returns with Other != -1, then the returned comparison
  is an or of two simpler comparisons.

However for at least the last five years this routine has never
returned a value of Other != -1; these cases are now handled
differently to begin with.

This patch removes the parameter and the code in SelectSETCC that
attempted to handle the Other != -1 case.

llvm-svn: 185541

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185540

This changes behavior of -msan-poison-stack=0 flag from not poisoning stack
allocations to actively unpoisoning them.

llvm-svn: 185538

[PowerPC] Make specialized AltiVec patterns isCodeGenOnly

A couple of AltiVec patterns are just specialized forms of the
generic instruction pattern, and should therefore be marked
isCodeGenOnly to avoid confusing the asm parser:
VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES.

Noticed by inspection of the generated PPCGenAsmMatcher.inc.

llvm-svn: 185533

[PowerPC] Support mtspr/mfspr in the asm parser

This adds support for the generic forms of mtspr/mfspr
for the asm parser.  The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.

llvm-svn: 185532

Add a mapping from register-based <INSN>R instructions to the corresponding
memory-based <INSN>.  Use it to cut down on the number of spill loads.

Some instructions extend their operands from smaller fields, so this
required a new TSFlags field to say how big the unextended operand is.

This optimisation doesn't trigger for C(G)R and CL(G)R because in practice
we always combine those instructions with a branch.  Adding a test for every
other case probably seems excessive, but it did catch a missed optimisation
for DSGF (fixed in r185435).

llvm-svn: 185529

1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits

llvm-svn: 185528

Swift cores implement store barriers that are stronger than the ARM
specification but weaker than general barriers. They are, in fact, just about
enough to provide the ordering needed for atomic operations with release
semantics.

This patch makes use of that quirk.

llvm-svn: 185527

Rename Function->DispKey and PairType->DispSize.  I'd originally used
"Function" because I thought it might be useful for other InstMappings.
However, it turns out that having two very similar instructions with the
same Function makes it pretty useless for anything other than the displacement
size key.  Other InstMappings will want the key to be defined for only one
instruction in the pair.

No behavioural change intended.

llvm-svn: 185526

Get rid of some old code (and associated FIXME) for handling the
caller-allocated register save area.  No behavioural change intended.

llvm-svn: 185525

llvm-svn: 185523

llvm-svn: 185520

llvm-svn: 185519

Patch by Robert Lytton.

llvm-svn: 185518

llvm-svn: 185514

llvm-svn: 185513

Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily.

llvm-svn: 185512

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185509

Introduce some typedefs for DenseMaps containing SmallVectors so the vector size doesn't have to repeated when creating iterators for the DenseMap.

llvm-svn: 185508

Return SmallVectorImpl& instead of SmallVector& in a couple places to avoid having to specify the vector size in multiple places.

llvm-svn: 185507

Use SmallVectorImpl& instead of SmallVector& to avoid needlessly respecifying the small vector size.

llvm-svn: 185505

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185504

Added support in FunctionAttrs for adding relevant function/argument attributes for the posix call gettimeofday.

This implies annotating it as nounwind and its arguments as nocapture. To be
conservative, we do not annotate the arguments with noalias since some platforms
do not have restrict on the declaration for gettimeofday.

llvm-svn: 185502

*NOTE* In a recent version of posix, they added the restrict keyword to the
arguments for this function. From some spelunking it seems that on some
platforms, the call has restrict on its arguments and others it does not. Thus I
left off the restrict keyword from the function prototype in the comment.

llvm-svn: 185501

avoid adding information for the debug_inlined section when it isn't
going to be emitted anyhow.

llvm-svn: 185500

llvm-svn: 185499

llvm-svn: 185498

llvm-svn: 185497

grep.

llvm-svn: 185496

llvm-svn: 185495