Commits · 271a5c72a0f43f8da540800dba016f5d1337c997 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Dec 14, 2017
- [X86] Remove redundant setOperationAction calls. · 271a5c72
  Craig Topper authored Dec 14, 2017
  271a5c72
- Recommit r320461 "[X86] Use regular expressions more aggressively to reduce... · f82867c9
  Craig Topper authored Dec 13, 2017
  f82867c9
Dec 13, 2017
- CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value · a5315a04
  Yaxun Liu authored Dec 13, 2017
  a5315a04
- Recover some overzealously removed includes. · 67b04bd8
  Michael Zolotukhin authored Dec 13, 2017
  67b04bd8
- Remove redundant includes from lib/Target/X86. · ad24af7f
  Michael Zolotukhin authored Dec 13, 2017
  ad24af7f
- Remove redundant includes from lib/Target/ARM. · caf9ea6a
  Michael Zolotukhin authored Dec 13, 2017
  caf9ea6a
- Remove redundant includes from lib/Target/AArch64. · a859bd9c
  Michael Zolotukhin authored Dec 13, 2017
  a859bd9c
- Remove redundant includes from lib/Target/*.cpp. · eb905c7e
  Michael Zolotukhin authored Dec 13, 2017
  eb905c7e
- AMDGPU: Partially fix disassembly of MIMG instructions · cad7fa85
  Matt Arsenault authored Dec 13, 2017
  cad7fa85
- Fix link failure on one build bot introduced by r320584. · 6af75240
  Nemanja Ivanovic authored Dec 13, 2017
  6af75240
- Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win. · 9dee3f0a
  Galina Kistanova authored Dec 13, 2017
  9dee3f0a
- [PowerPC] MachineSSA pass to reduce the number of CR-logical operations · 6f590bf8
  Nemanja Ivanovic authored Dec 13, 2017
  6f590bf8
- [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule tests · f00ea1b4
  Simon Pilgrim authored Dec 13, 2017
  f00ea1b4
- [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools · 845e5dce
  Alex Bradbury authored Dec 13, 2017
  845e5dce
- [X86][SSE] MOVMSK only uses the sign bit from each vector element · f51f4d36
  Simon Pilgrim authored Dec 13, 2017
  f51f4d36
- [RISCV] Implement floating point assembler pseudo instructions · fa7e4ec8
  Alex Bradbury authored Dec 13, 2017
  fa7e4ec8
- [mips] Provide additional DSP bitconvert patterns · 0a075d68
  Stefan Maksimovic authored Dec 13, 2017
  0a075d68
- [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention · 19c9314a
  Alex Bradbury authored Dec 13, 2017
  19c9314a
- [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted position · 581d6b08
  Alex Bradbury authored Dec 13, 2017
  581d6b08
- [RISCV] MC layer support for the remaining RVC instructions · 60714f98
  Alex Bradbury authored Dec 13, 2017
  60714f98
- [Targets] Don't automatically include the scheduler class enum from... · ac59db2e
  Craig Topper authored Dec 13, 2017
  ac59db2e
- Rename LiveIntervalAnalysis.h to LiveIntervals.h · f842297d
  Matthias Braun authored Dec 13, 2017
  f842297d
Dec 12, 2017
- [Hexagon] Better detection of identity and undef masks in shuffles · edcd9dcb
  Krzysztof Parzyszek authored Dec 12, 2017
  edcd9dcb
- [Hexagon] Fix wrong order of operands for vmux · 40a605f1
  Krzysztof Parzyszek authored Dec 12, 2017
  40a605f1
- Reapply "[X86] Flag BroadWell scheduler model as complete" · 1074eb22
  Sanjoy Das authored Dec 12, 2017
  1074eb22
- Revert "[X86] Flag BroadWell scheduler model as complete" · 81a4a02c
  Sanjoy Das authored Dec 12, 2017
  81a4a02c
- [X86] Add a couple TODOs about missing coverage/features motivated by D40335 · 712a209d
  Craig Topper authored Dec 12, 2017
  712a209d
- [X86] Cleanup type conversion of 64-bit load-store pairs. · 674d053d
  Nirav Dave authored Dec 12, 2017
  674d053d
- [MachineOperand][MIR] Add isRenamable to MachineOperand. · 60c43102
  Geoff Berry authored Dec 12, 2017
  60c43102
- [X86] Remove CompleteModel tags from CPU targets until we have better error checking (PR35636) · 68f9accf
  Simon Pilgrim authored Dec 12, 2017
  68f9accf
- [RISCV][NFC] Formatting fix in RISCVInstrInfo.td · c01db1ce
  Alex Bradbury authored Dec 12, 2017
  c01db1ce
- [RISCV] Implement assembler pseudo instructions for RV32I and RV64I · 9ed84c8a
  Alex Bradbury authored Dec 12, 2017
  9ed84c8a
- [RISCV] MC layer support for the instructions added in the privileged spec · 8bba6bfe
  Alex Bradbury authored Dec 12, 2017
  8bba6bfe
- [X86] Recognize constant arrays with special values and replace loads from it... · c2eed926
  Ayman Musa authored Dec 12, 2017
  c2eed926
- [PowerPC] Add branch flag on asm parser-only branch instructions · 6479c72f
  Nemanja Ivanovic authored Dec 12, 2017
  6479c72f
- [PowerPC] Follow-up to r318436 to get the missed CSE opportunities · b0783ccc
  Nemanja Ivanovic authored Dec 12, 2017
  b0783ccc
- Revert r320461 - causing ICE in windows buildss · 0f8a5a41
  Simon Pilgrim authored Dec 12, 2017
  0f8a5a41
- [X86] Use regular expressions more aggressively to reduce the number of... · c8e64ab5
  Craig Topper authored Dec 12, 2017
  c8e64ab5
- [X86] Use Ld scheduler classes for instructions with folded loads. · 468a8133
  Craig Topper authored Dec 12, 2017
  468a8133
- [X86] Correct the FMA3 regular expressions in the znver1 scheduler model. · c1e72c01
  Craig Topper authored Dec 12, 2017
  c1e72c01