they make it less convenient to add new entries.

llvm-svn: 83308

is used in an operand which requires GR64_NOREX.

llvm-svn: 83307

the new predicates I added) instead of going through a context and doing a
pointer comparison.  Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.

llvm-svn: 83297

llvm-svn: 83257

Thanks to Johnny Chen for pointing this out!

llvm-svn: 83256

llvm-svn: 83242

llvm-svn: 83237

llvm-svn: 83236

Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.

llvm-svn: 83218

Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.

llvm-svn: 83215

llvm-svn: 83214

ld / st pairs, etc.

llvm-svn: 83197

llvm-svn: 83192

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

This will allow processDebugLoc() to handle scopes for DWARF debug info. 

llvm-svn: 83183

Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.

llvm-svn: 83178

to emit target-specific things at the beginning of the asm output.  This
fixes a problem for PPC, where the text sections are not being kept together
as expected.  The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives.  The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text.  With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.

llvm-svn: 83176

llvm-svn: 83174

for derived AsmPrinters to add another one.  In some cases, fixing this
removes the need to override the doInitialization method.

llvm-svn: 83170

llvm-svn: 83148

llvm-svn: 83145

the size of the saved frame pointer needs to be taken into account.

llvm-svn: 83136

Patch by Sylvere Teissier.

llvm-svn: 83135

section directives.  This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations.  Radar 7255355.

llvm-svn: 83127

Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.

llvm-svn: 83122

llvm-svn: 83117

llvm-svn: 83083

llvm-svn: 83058

slot for the register scavenger when compiling Thumb1 functions.

llvm-svn: 83023

llvm-svn: 83008

unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006

Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988

instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982

Disable rematting of it for now.

llvm-svn: 82975

This should be better than single load from constpool.

llvm-svn: 82948

operand is now at index 2, rather than 3. This fixes the
"Invalid child # of SDNode!" failures on PowerPC.

llvm-svn: 82942

llvm-svn: 82909

llvm-svn: 82893

llvm-svn: 82838

llvm-svn: 82837