CBE and interpreter.

llvm-svn: 31755

llvm-svn: 31753

llvm-svn: 31712

  will be inserted before these operands. If the opcode changes (by
  setOpcode), the implicit operands are updated as well.
- Added IsKill, IsDead fields to MachineOperand in preparation for changes
  that move kill / dead info to MachineInstr's.

llvm-svn: 31711

llvm-svn: 31686

llvm-svn: 31675

pass to explode.  This fixes a bunch of llc-beta failures on ppc last night.

llvm-svn: 31661

llvm-svn: 31660

llvm-svn: 31658

CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast

llvm-svn: 31644

llvm-svn: 31633

When forming a pre-indexed store, make sure ptr isn't the same or is a pred of value being stored. It would cause a cycle.

llvm-svn: 31631

llvm-svn: 31627

llvm-svn: 31598

llvm-svn: 31597

llvm-svn: 31596

llvm-svn: 31595

llvm-svn: 31594

llvm-svn: 31593

llvm-svn: 31584

llvm-svn: 31583

llvm-svn: 31569

llvm-svn: 31561

llvm-svn: 31549

  about whether the new base ptr would be live below the load/store. Let two
  address pass split it back to non-indexed ops.
- Minor tweaks / fixes.

llvm-svn: 31544

llvm-svn: 31543

This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.

llvm-svn: 31542

llvm-svn: 31537

LBB1_57:        #bb207.i
        movl 72(%esp), %ecx
        movb (%ecx,%eax), %cl
        movl 80(%esp), %edx
        movb %cl, 1(%edx,%eax)
        incl %eax
        cmpl $143, %eax
        jne LBB1_57     #bb207.i
        jmp LBB1_64     #cond_next255.i

intead of:

LBB1_57:        #bb207.i
        movl 72(%esp), %ecx
        movb (%ecx,%eax), %cl
        movl 80(%esp), %edx
        movb %cl, 1(%edx,%eax)
        incl %eax
        cmpl $143, %eax
        je LBB1_64      #cond_next255.i
        jmp LBB1_57     #bb207.i

This eliminates a branch per iteration of the loop.  This hurted PPC
particularly, because the extra branch meant another dispatch group for each
iteration of the loop.

llvm-svn: 31530

llvm-svn: 31516

llvm-svn: 31514

llvm-svn: 31512

empty ranges.

2. Reorg how MachineDebugInfo maintains changes to debug labels.

3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.

4. Revert the merging of compile units until I can get the bugs ironed out.

llvm-svn: 31507

by 40%, FreeBench/fourinarow by 20%, and many other programs 10-25%.

On PPC, this speeds up fourinarow by 18%, and probably other things as well.

llvm-svn: 31504

llvm-svn: 31500

llvm-svn: 31498

X86.  If happy, I'll enable this by default.

llvm-svn: 31493

llvm-svn: 31492

The low part goes in the first operand of expandop, not the second one.

llvm-svn: 31487

llvm-svn: 31478