Commits · 2787efd961ea078bc7434ce13e0e6d96881a5fdc · Roger Ferrer / llvm-epi-0.8

Jun 19, 2010
- Remove unnecessary arguments · 2787efd9
  Bruno Cardoso Lopes authored Jun 19, 2010
```
llvm-svn: 106371
```
  2787efd9
- Add AVX packed intrinsics for MIN, MAX · 00ada89f
  Bruno Cardoso Lopes authored Jun 19, 2010
```
llvm-svn: 106370
```
  00ada89f
- Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions · 1e205f6b
  Bruno Cardoso Lopes authored Jun 19, 2010
```
llvm-svn: 106366
```
  1e205f6b
- Clean up: remove now unnecessary Constraints · 1888f118
  Bruno Cardoso Lopes authored Jun 19, 2010
```
llvm-svn: 106361
```
  1888f118
- more refactoring! yay! big win over the intrinsics · 502c4fe6
  Bruno Cardoso Lopes authored Jun 19, 2010
```
llvm-svn: 106359
```
  502c4fe6
- Apply some refactor to packed instructions · 2bfad417
  Bruno Cardoso Lopes authored Jun 18, 2010
```
llvm-svn: 106349
```
  2bfad417
- Use the new 'defm' class inheritance in SSE · 871439ab
  Bruno Cardoso Lopes authored Jun 18, 2010
```
llvm-svn: 106327
```
  871439ab
Jun 18, 2010
- Add {mix,max}{ss,sd}{rr,rm} AVX forms. · 23231687
  Bruno Cardoso Lopes authored Jun 18, 2010
```
llvm-svn: 106264
```
  23231687
- Use new tablegen resources in SSE tablegen code. This will · 6b98f712
  Bruno Cardoso Lopes authored Jun 17, 2010
```
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction

llvm-svn: 106251
```
  6b98f712
Jun 12, 2010
- make the avx intrinsics 3 address · ada854f8
  Bruno Cardoso Lopes authored Jun 12, 2010
```
llvm-svn: 105876
```
  ada854f8
- Add some basic fp intrinsics for AVX · f2037034
  Bruno Cardoso Lopes authored Jun 12, 2010
```
llvm-svn: 105873
```
  f2037034
- More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm · a714ea0f
  Bruno Cardoso Lopes authored Jun 12, 2010
```
llvm-svn: 105870
```
  a714ea0f
- More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr · b06f54b8
  Bruno Cardoso Lopes authored Jun 12, 2010
```
Handle OpSize TSFlag for AVX

llvm-svn: 105869
```
  b06f54b8
- More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) · fd5458d4
  Bruno Cardoso Lopes authored Jun 11, 2010
```
Introduce the VEX_X field

llvm-svn: 105859
```
  fd5458d4
Jun 09, 2010
- Reapply r105521, this time appending "LLU" to 64 bit · c2f87b7b
  Bruno Cardoso Lopes authored Jun 08, 2010
```
immediates to avoid breaking the build.

llvm-svn: 105652
```
  c2f87b7b
Jun 05, 2010

revert r105521, which is breaking the buildbots with stuff like this: · fdd26143

Chris Lattner authored Jun 05, 2010

In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524

fdd26143

Initial AVX support for some instructions. No patterns matched · 594fa263
Bruno Cardoso Lopes authored Jun 05, 2010
```
yet, only assembly encoding support.

llvm-svn: 105521
```
594fa263

Jun 01, 2010
- Refactor some SSE 2 unpack instructions · d44677ba
  Bruno Cardoso Lopes authored Jun 01, 2010
```
llvm-svn: 105276
```
  d44677ba
May 29, 2010
- More SSE 1 & 2 merge, this time with logical instructions · 1f792898
  Bruno Cardoso Lopes authored May 28, 2010
```
llvm-svn: 105014
```
  1f792898
May 27, 2010
- Merge basic binops SSE 1 & 2 instruction classes. This is a step towards refactoring · 54b07ad2
  Bruno Cardoso Lopes authored May 27, 2010
```
common code between SSE versions.

llvm-svn: 104860
```
  54b07ad2
May 26, 2010
- Fix a typo in a comment that Gabor noticed. · 338674a3
  Dan Gohman authored May 26, 2010
```
llvm-svn: 104711
```
  338674a3
May 25, 2010
- MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. · 4a5b2c59
  Daniel Dunbar authored May 25, 2010
```
llvm-svn: 104622
```
  4a5b2c59
- Make sure aeskeygenassist uses an unsigned immediate field. · f6562d35
  Eric Christopher authored May 25, 2010
```
Fixes rdar://8017638

llvm-svn: 104617
```
  f6562d35
May 24, 2010
- Rename X86 subregister indices to something shorter. · 9340ea59
  Jakob Stoklund Olesen authored May 24, 2010
```
Use the tablegen-produced enums.

llvm-svn: 104493
```
  9340ea59
May 20, 2010
- Define the x86 pause instruction. · 1e19eab9
  Dan Gohman authored May 20, 2010
```
llvm-svn: 104204
```
  1e19eab9
- Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it · a3b7570a
  Dan Gohman authored May 20, 2010
```
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

llvm-svn: 104203
```
  a3b7570a
Apr 20, 2010
- Remove the palignr intrinsics now that we lower them to vector shuffles, · 64831c6a
  Eric Christopher authored Apr 20, 2010
```
shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.

llvm-svn: 101851
```
  64831c6a
Apr 17, 2010
- a bunch of ssse3 instructions are misencoded to think they have an · 7f5088e6
  Chris Lattner authored Apr 17, 2010
```
i8 field when they really do not.  This fixes rdar://7840289

llvm-svn: 101629
```
  7f5088e6
Apr 15, 2010
- Allow lowering for palignr instructions for mmx sized vectors. Add · eabc9623
  Eric Christopher authored Apr 15, 2010
```
patterns to handle the lowering.

llvm-svn: 101331
```
  eabc9623
Apr 08, 2010
- mpsadbw is not commutative. · c0f63cf7
  Eric Christopher authored Apr 08, 2010
```
Fixes PR3440.

llvm-svn: 100736
```
  c0f63cf7
Apr 03, 2010
- Rewrite aesimc handling. It only takes a single input and has a single · 000e502e
  Eric Christopher authored Apr 02, 2010
```
dest.

llvm-svn: 100252
```
  000e502e
Apr 02, 2010

Separate out the AES-NI instructions from the SSE4.2 instructions. Add · 2ef63183

Eric Christopher authored Apr 02, 2010

a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.

llvm-svn: 100231

2ef63183

Apr 01, 2010

Add aeskeygenassist intrinsic and rename all of the aes intrinsics to · 9002ac5d

Eric Christopher authored Apr 01, 2010

aes instead of sse4.2.  Add a brief todo for a subtarget flag and rework
the aeskeygenassist instruction to more closely match the docs.

llvm-svn: 100078

9002ac5d

Mar 31, 2010
- Replace V_SET0 with variants for each SSE execution domain. · 9986ba95
  Jakob Stoklund Olesen authored Mar 31, 2010
```
llvm-svn: 99975
```
  9986ba95
- V_SETALLONES is an integer instruction. · 3493398f
  Jakob Stoklund Olesen authored Mar 30, 2010
```
Since it is just a pxor in disguise, we should probably expand it to a full
polymorphic triple.

llvm-svn: 99953
```
  3493398f
Mar 30, 2010
- Remove the pmulld intrinsic and autoupdate it as a vector multiply. · 6ad81677
  Eric Christopher authored Mar 30, 2010
```
Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.

llvm-svn: 99910
```
  6ad81677
Mar 29, 2010
- We'll never match these as instructions, just as intrinsics so remove · 9bdadf0d
  Eric Christopher authored Mar 29, 2010
```
the SDNodes.

llvm-svn: 99835
```
  9bdadf0d
Mar 28, 2010
- zap an extra line that Eli noticed! · 11f85ccf
  Chris Lattner authored Mar 28, 2010
```
llvm-svn: 99770
```
  11f85ccf
- remove a pattern with no testcase that doesn't appear to be · 505849d2
  Chris Lattner authored Mar 28, 2010
```
matchable: it seems like it would always constant fold.

llvm-svn: 99758
```
  505849d2
- fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest · ec5fe658
  Chris Lattner authored Mar 28, 2010
```
nodes all have an EFLAGS result when made by isel lowering.

llvm-svn: 99736
```
  ec5fe658