llvm-svn: 31267

llvm-svn: 31266

the pred block doesn't fall through into them if it's a jumptable.

llvm-svn: 31263

llvm-svn: 31261

being inserted on unsplit critical edges, which introduces (sometimes large
amounts of) partially dead spill code.

This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll

llvm-svn: 31260

llvm-svn: 31254

llvm-svn: 31243

Add many fewer CFG edges and PHI node entries.  If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)

llvm-svn: 31242

llvm-svn: 31240

llvm-svn: 31233

        cmpwi cr0, r4, 4
        bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
        cmplwi cr0, r3, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r3, r4, r3
        rlwinm r2, r2, 30, 31, 31
        or r2, r2, r3
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true

llvm-svn: 31232

This compiles Regression/CodeGen/X86/or-branch.ll into:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $5, %eax
        jl LBB1_1       #cond_true
LBB1_3: #entry
        testl %ecx, %ecx
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

instead of:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $4, %eax
        setg %al
        testl %ecx, %ecx
        setne %cl
        testb %cl, %al
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

And on ppc to:

        cmpwi cr0, r29, 5
        blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
        cmplwi cr0, r30, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r30, r4, r3
        rlwinm r29, r2, 30, 31, 31
        and r2, r29, r30
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

llvm-svn: 31230

llvm-svn: 31209

Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.

llvm-svn: 31195

llvm-svn: 31188

llvm-svn: 31180

llvm-svn: 31179

llvm-svn: 31171

visitBr to just call visitSwitchCase, eliminating duplicate logic.

llvm-svn: 31167

Rename LHSBB/RHSBB to TrueBB/FalseBB.  Allow the RHS value to be null,
in which case the LHS is treated as a bool.

llvm-svn: 31166

llvm-svn: 31161

llvm-svn: 31155

llvm-svn: 31153

llvm-svn: 31152

a place more useful.  In particular, if we can put them in a place where code
will be able to fall into it, do so.  Otherwise, put it in a place it can fall
through into a successor.  Otherwise, if preventing a fallthrough, move to the
end of the function, out of the way.

This deletes several hundred unconditional branches from spass.

llvm-svn: 31149

llvm-svn: 31145

llvm-svn: 31140

        movl 32(%esp), %eax
        cmpl $1, %eax
        je LBB1_1       #bb
LBB1_4: #entry
        cmpl $2, %eax
        je LBB1_2       #bb2
        jmp LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb

notice that we would miss the fall through and emit this instead:

        movl 32(%esp), %eax
        cmpl $2, %eax
        je LBB1_2       #bb2
LBB1_4: #entry
        cmpl $1, %eax
        jne LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb

llvm-svn: 31130

llvm-svn: 31129

llvm-svn: 31125

llvm-svn: 31124

llvm-svn: 31119

llvm-svn: 31102

        call L_strcmp$stub
        testl %eax, %eax
-       jne LBB26_208   #cond_true6020
-       jmp LBB26_227   #bb7119
+       je LBB26_227    #bb7119
 LBB26_208:     #cond_true6020
        movl $l31_str14, 4(%esp)

        testl %eax, %eax
-       jne LBB26_704   #cond_true13042
-       jmp LBB26_713   #bb13151
+       je LBB26_713    #bb13151
 LBB26_704:     #cond_true13042
        movl $_str52, 4(%esp)

        cmpl 76(%ecx), %eax
-       jge LBB26_1628  #cond_false63.i.i
-       jmp LBB26_1769  #_Z8makeGridP13mrSurfaceListidiidd.exit.i
+       jl LBB26_1769   #_Z8makeGridP13mrSurfaceListidiidd.exit.i
 LBB26_1628:    #cond_false63.i.i
        movl $0, 48964(%esp)

llvm-svn: 31100

  jle FOO
  jmp BAR
BAR:

into:

  jle FOO
BAR:

... whoa!

llvm-svn: 31098

1. Remove a bunch of ifdef'd code.
2. When a block just contains an uncond branch, change all blocks branching
   to it to jump to the destination instead.
3. If branch analysis tells us some edges in the machinecfg are not actually
   possible, remove them.

#2 triggers a suprisingly large number of times.

llvm-svn: 31094

This is currently disabled by default and limited in several ways, but does
have a positive effect.

llvm-svn: 31090

llvm-svn: 31088

output.

llvm-svn: 31067

This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.

llvm-svn: 31063