llvm-svn: 141116

When resolving an operator list element reference, resolve all
operator operands and try to fold the operator first.  This allows the
operator to collapse to a list which may then be indexed.

Before, it was not possible to do this:
class D<int a, int b> { ... }
class C<list<int> A> : D<A[0], A[1]>;
class B<list<int> b> : C<!foreach(...,b)>;

Now it is.

llvm-svn: 141101

llvm-svn: 141097

Put GCOVFile and other related interface in a common header so that llvm-cov tool can share it with GCOV writer.

llvm-svn: 141095

llvm-svn: 141093

This has already been done for most other targets.

llvm-svn: 141083

This patch adds a preprocessor that can expand nested for-loops for
saving some copy-n-paste in *.td files.

The preprocessor is not yet integrated with TGParser, and so it has
no direct effect on *.td inputs.  However, you may preprocess an td
input (and only preprocess it).

To test the proprecessor, type:
  tblgen -E -o $@ $<

llvm-svn: 141079

llvm-svn: 141075

Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074

llvm-svn: 141066

Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.

llvm-svn: 141065

This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"

llvm-svn: 141059

llvm-svn: 141058

llvm-svn: 141057

llvm-svn: 141050

llvm-svn: 141046

llvm-svn: 141043

Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.

llvm-svn: 141042

llvm-svn: 141040

llvm-svn: 141038

llvm-svn: 141032

This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.

llvm-svn: 141031

llvm-svn: 141029

llvm-svn: 141028

Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair.

llvm-svn: 141026

llvm-svn: 141025

llvm-svn: 141024

llvm-svn: 141023

It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.

llvm-svn: 141020

registers.

llvm-svn: 141019

llvm-svn: 141017

registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015

Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.

llvm-svn: 141007

llvm-svn: 141005

llvm-svn: 141004

llvm-svn: 141001

Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.

llvm-svn: 140997

llvm-svn: 140993

logic by David Meyer revealed this bug.

llvm-svn: 140992

llvm-svn: 140980