Commits · 28c5b8618a58a8fdc7a7f2505a7aa367b35fc129 · Roger Ferrer / llvm-epi-0.8

Nov 28, 2006
- Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead · 20350c40
  Evan Cheng authored Nov 27, 2006
```
of opcode and number of operands.

llvm-svn: 31947
```
  20350c40
Oct 24, 2006
- fix warning about missing newline at end of file · ed32883b
  Rafael Espindola authored Oct 24, 2006
```
llvm-svn: 31162
```
  ed32883b
- implement uncond branch insertion, mark branches with isBranch. · aaeede0a
  Chris Lattner authored Oct 24, 2006
```
llvm-svn: 31160
```
  aaeede0a
Sep 13, 2006
- add shifts to addressing mode 1 · 3130a756
  Rafael Espindola authored Sep 13, 2006
```
llvm-svn: 30291
```
  3130a756
Sep 11, 2006
- partial implementation of the ARM Addressing Mode 1 · e45a79a9
  Rafael Espindola authored Sep 11, 2006
```
llvm-svn: 30252
```
  e45a79a9
Aug 08, 2006
- change the addressing mode of the str instruction to reg+imm · 8c41f99e
  Rafael Espindola authored Aug 08, 2006
```
llvm-svn: 29571
```
  8c41f99e
Jul 10, 2006

create the raddr addressing mode that matches any register and the frame index · e40a7e2a

Rafael Espindola authored Jul 10, 2006

use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079

e40a7e2a

Jun 27, 2006
- handle the "mov reg1, reg2" case in isMoveInstr · f6f5aff0
  Rafael Espindola authored Jun 27, 2006
```
llvm-svn: 28945
```
  f6f5aff0
May 23, 2006

implement minimal versions of · 27f8bdc7

Rafael Espindola authored May 23, 2006

ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr

llvm-svn: 28431

27f8bdc7

May 15, 2006
- added a skeleton of the ARM backend · ffdc24b8
  Rafael Espindola authored May 14, 2006
```
llvm-svn: 28301
```
  ffdc24b8