llvm-svn: 134645

based on a modifier, split it into two functions.

llvm-svn: 134637

before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625

llvm-svn: 133494

llvm-svn: 132777

dynamically allocated stack area was not set.

llvm-svn: 132758

llvm-svn: 132717

nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323

Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322

Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240

llvm-svn: 132063

offsets that are larger than 0x10000.

llvm-svn: 132003

llvm-svn: 131233

Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086

llvm-svn: 130131

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

llvm-svn: 128650

llvm-svn: 127034

Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka

llvm-svn: 127032

llvm-svn: 127027

llvm-svn: 127005

llvm-svn: 127003

llvm-svn: 123760

llvm-svn: 122513

llvm-svn: 121377

Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again

llvm-svn: 121164

(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.

llvm-svn: 121163

llvm-svn: 118864

llvm-svn: 118667

llvm-svn: 118515

llvm-svn: 111468

llvm-svn: 111241

llvm-svn: 106465

need them.

llvm-svn: 98937

llvm-svn: 97374

llvm-svn: 96504

in hte generated dag isel fil.

llvm-svn: 96193

the instruction to load those args removed. This fix PR6071

llvm-svn: 93880

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517