llvm-svn: 36031

define i32 @test(float %f) {
        %tmp7 = insertelement <4 x float> undef, float %f, i32 0
        %tmp17 = bitcast <4 x float> %tmp7 to <4 x i32>
        %tmp19 = extractelement <4 x i32> %tmp17, i32 0
        ret i32 %tmp19
}

into:

define i32 @test(float %f) {
        %tmp19 = bitcast float %f to i32                ; <i32> [#uses=1]
        ret i32 %tmp19
}

On PPC, this is the difference between:

_test:
        mfspr r2, 256
        oris r3, r2, 8192
        mtspr 256, r3
        stfs f1, -16(r1)
        addi r3, r1, -16
        addi r4, r1, -32
        lvx v2, 0, r3
        stvx v2, 0, r4
        lwz r3, -32(r1)
        mtspr 256, r2
        blr

and:

_test:
        stfs f1, -4(r1)
        nop
        nop
        nop
        lwz r3, -4(r1)
        blr

llvm-svn: 36025

unsigned test(float f) {
 return _mm_cvtsi128_si32( (__m128i) _mm_set_ss( f*f ));
}

into:

_test:
        movss 4(%esp), %xmm0
        mulss %xmm0, %xmm0
        movd %xmm0, %eax
        ret

instead of:

_test:
        movss 4(%esp), %xmm0
        mulss %xmm0, %xmm0
        xorps %xmm1, %xmm1
        movss %xmm0, %xmm1
        movd %xmm1, %eax
        ret

GCC gets:

_test:
        subl    $28, %esp
        movss   32(%esp), %xmm0
        mulss   %xmm0, %xmm0
        xorps   %xmm1, %xmm1
        movss   %xmm0, %xmm1
        movaps  %xmm1, %xmm0
        movd    %xmm0, 12(%esp)
        movl    12(%esp), %eax
        addl    $28, %esp
        ret

llvm-svn: 36020

llvm-svn: 35981

llvm-svn: 35979

out to do! :)

This fixes a problem where LSR would insert a bunch of code into each MBB
that uses a particular subexpression (e.g. IV+base+C).  The problem is that
this code cannot be CSE'd back together if inserted into different blocks.

This patch changes LSR to attempt to insert a single copy of this code and
share it, allowing codegenprepare to duplicate the code if it can be sunk
into various addressing modes.  On CodeGen/ARM/lsr-code-insertion.ll,
for example, this gives us code like:

        add r8, r0, r5
        str r6, [r8, #+4]
..
        ble LBB1_4      @cond_next
LBB1_3: @cond_true
        str r10, [r8, #+4]
LBB1_4: @cond_next
...
LBB1_5: @cond_true55
        ldr r6, LCPI1_1
        str r6, [r8, #+4]

instead of:

        add r10, r0, r6
        str r8, [r10, #+4]
...
        ble LBB1_4      @cond_next
LBB1_3: @cond_true
        add r8, r0, r6
        str r10, [r8, #+4]
LBB1_4: @cond_next
...
LBB1_5: @cond_true55
        add r8, r0, r6
        ldr r10, LCPI1_1
        str r10, [r8, #+4]

Besides being smaller and more efficient, this makes it immediately
obvious that it is profitable to predicate LBB1_3 now :)

llvm-svn: 35972

this fixes problems where codegenprepare would sink expressions into load/stores
that are not valid, and fixes cases where it would miss important valid ones.

This fixes several serious codesize and perf issues, particularly on targets
with complex addressing modes like arm and x86.  For example, now we compile
CodeGen/X86/isel-sink.ll to:

_test:
        movl 8(%esp), %eax
        movl 4(%esp), %ecx
        cmpl $1233, %eax
        ja LBB1_2       #F
LBB1_1: #T
        movl $4, (%ecx,%eax,4)
        movl $141, %eax
        ret
LBB1_2: #F
        movl (%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl 8(%esp), %eax
        leal (,%eax,4), %ecx
        addl 4(%esp), %ecx
        cmpl $1233, %eax
        ja LBB1_2       #F
LBB1_1: #T
        movl $4, (%ecx)
        movl $141, %eax
        ret
LBB1_2: #F
        movl (%ecx), %eax
        ret

llvm-svn: 35970

llvm-svn: 35906

        icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
        sext i1 %0 to i32               ; <i32>:1 [#uses=1]

into:

        %X.lobit = ashr i32 %X, 31              ; <i32> [#uses=1]

This implements InstCombine/icmp.ll:test[34]

llvm-svn: 35891

Transforms/InstCombine/icmp.ll

llvm-svn: 35890

llvm-svn: 35886

define i32 @test(i32 %X) {
entry:
        %Y = and i32 %X, 4              ; <i32> [#uses=1]
        icmp eq i32 %Y, 0               ; <i1>:0 [#uses=1]
        sext i1 %0 to i32               ; <i32>:1 [#uses=1]
        ret i32 %1
}

by moving code out of commonIntCastTransforms into visitZExt.  Simplify the
APInt gymnastics in it etc.

llvm-svn: 35885

llvm-svn: 35879

We now tolerate small amounts of undefined behavior, better emulating what
would happen if the transaction actually occurred in memory.  This fixes
SingleSource/UnitTests/2007-04-10-BitfieldTest.c on PPC, at least until
Devang gets a chance to fix the CFE from doing undefined things with bitfields :)

llvm-svn: 35875

InstCombine/set.ll:test25

llvm-svn: 35852

llvm-svn: 35844

llvm-svn: 35837

llvm-svn: 35836

happen to be an entry, in such case, it is not a good idea to
insert new block before entry.

Also fix typo in assertion check.

llvm-svn: 35833

llvm-svn: 35829

llvm-svn: 35825

llvm-svn: 35822

Handle Argument or Undef as an incoming PHI value.

llvm-svn: 35821

llvm-svn: 35820

llvm-svn: 35819

llvm-svn: 35792

Transforms/InstCombine/vec_insertelt.ll and fixes PR1286.

We now compile the code from that bug into:

_foo:
        movl 4(%esp), %eax
        movdqa (%eax), %xmm0
        movl 8(%esp), %ecx
        psllw (%ecx), %xmm0
        movdqa %xmm0, (%eax)
        ret

instead of:

_foo:
        subl $4, %esp
        movl %ebp, (%esp)
        movl %esp, %ebp
        movl 12(%ebp), %eax
        movdqa (%eax), %xmm0
        #IMPLICIT_DEF %eax
        pinsrw $2, %eax, %xmm0
        xorl %ecx, %ecx
        pinsrw $3, %ecx, %xmm0
        pinsrw $4, %eax, %xmm0
        pinsrw $5, %ecx, %xmm0
        pinsrw $6, %eax, %xmm0
        pinsrw $7, %ecx, %xmm0
        movl 8(%ebp), %eax
        movdqa (%eax), %xmm1
        psllw %xmm0, %xmm1
        movdqa %xmm1, (%eax)
        movl %ebp, %esp
        popl %ebp
        ret

woo :)

llvm-svn: 35788

llvm-svn: 35765

llvm-svn: 35763

Add a new xform to simplify (A&B)|(~A&C).  THis implements InstCombine/or2.ll:test1

llvm-svn: 35760

llvm-svn: 35734

llvm-svn: 35731

llvm-svn: 35724

llvm-svn: 35719

llvm-svn: 35718

first and then range testing second.

llvm-svn: 35715

llvm-svn: 35714

llvm-svn: 35700

llvm-svn: 35680

elsewhere.

llvm-svn: 35668