implicit defs get added to the end of machine instrs sometimes.  Scan the whole instruction for the metadata operand instead of assuming it will be at the end of the instruction.

llvm-svn: 100792

llvm-svn: 100789

llvm-svn: 100787

There is no need to remember labels identifying regions marked by such instructions in each scope.

llvm-svn: 100781

llvm-svn: 100780

llvm-svn: 100774

llvm-svn: 100771

llvm-svn: 100769

llvm-svn: 100768

llvm-svn: 100767

llvm-svn: 100762

llvm-svn: 100760

llvm-svn: 100758

llvm-svn: 100756

llvm-svn: 100751

undef as 0, since it can't force other analyses to intepret the undef
in the same way.

llvm-svn: 100749

ensure that the expansion is dominated by the increments of those loops.

llvm-svn: 100748

llvm-svn: 100742

Fixes PR3440.

llvm-svn: 100736

I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.

llvm-svn: 100735

so the user at least knows what inline asm is a problem.  For example:

error: inline asm not supported yet: don't know how to handle tied indirect register inputs
pr8788-1.c:14:10: note: generated from here
    asm ("\n" : "+r" (stack->regs)
         ^

Instead of:
fatal error: error in backend: Don't know how to handle tied indirect register inputs yet!

llvm-svn: 100731

llvm-svn: 100725

llvm-svn: 100724

and use it in one place in inline asm handling stuff.  Before
we'd generate this for an invalid modifier letter:

$ clang asm.c -c -o t.o
fatal error: error in backend: Invalid operand found in inline asm: 'abc incl    ${0:Z}'
INLINEASM <es:abc incl    ${0:Z}>, 10, %EAX<def>, 2147483657, %EAX, 14, %EFLAGS<earlyclobber,def,dead>, <!-1>


Now we generate this:

$ clang asm.c -c -o t.o
error: invalid operand in inline asm: 'incl    ${0:Z}'
asm.c:3:12: note: generated from here
  __asm__ ("incl    %Z0" : "+r" (X));
           ^
1 error generated.

This is much better but still admittedly not great ("why" is the operand 
invalid??), codegen should try harder with its diagnostics :)

llvm-svn: 100723

llvm-svn: 100720

and friends.

llvm-svn: 100717

llvm-svn: 100714

llvm-svn: 100713

llvm-svn: 100710

llvm-svn: 100709

llvm-svn: 100706

llvm-svn: 100703

llvm-svn: 100702

llvm-svn: 100700

explicitly split into stride-and-offset pairs. Also, add the
ability to track multiple post-increment loops on the same expression.

This refines the concept of "normalizing" SCEV expressions used for
to post-increment uses, and introduces a dedicated utility routine for
normalizing and denormalizing expressions.

This fixes the expansion of expressions which are post-increment users
of more than one loop at a time. More broadly, this takes LSR another
step closer to being able to reason about more than one loop at a time.

llvm-svn: 100699

llvm-svn: 100697

llvm-svn: 100696

Next to work on is ARMDisassemblerCore.cpp.

llvm-svn: 100695

argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.

llvm-svn: 100694

llvm-svn: 100693