of loops.

llvm-svn: 97642

llvm-svn: 97641

that are hidden by other derived base subobjects reached along a
lookup path that does *not* pass through the hiding subobject (C++
[class.member.lookup]p6). Fixes PR6462.

llvm-svn: 97640

llvm-svn: 97639

__builtin_frob_return_address.  The implementations for both are
still trivial in the default case.

llvm-svn: 97638

for the base destructor, because aliases to declarations aren't legal.

Fixes PR 6471.

llvm-svn: 97637

llvm-svn: 97635

level. No functionality change, and it obeys access control this
time.

llvm-svn: 97634

better done by dag combine.

llvm-svn: 97633

for disassembly only.

llvm-svn: 97632

llvm-svn: 97631

'dsload' pattern.  tblgen doesn't check patterns to see if they're
textually identical.  This allows better factoring.

llvm-svn: 97630

that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.

llvm-svn: 97629

- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628

llvm-svn: 97627

llvm-svn: 97626

llvm-svn: 97625

If an initializer in a DeclStmt references the declared variable, that
extends the liveness of that variable.

llvm-svn: 97624

llvm-svn: 97623

llvm-svn: 97621

(even if it is defined).  This fixes the issue of this function
returning '0' when SVN_VERSION is defined to be "".

Fixes: <rdar://problem/7663667>
llvm-svn: 97620

llvm-svn: 97619

static function. No functionality change.

llvm-svn: 97618

llvm-svn: 97617

long test(long x) { return (x & 123124) | 3; }

Currently compiles to:

_test:
        orl     $3, %edi
        movq    %rdi, %rax
        andq    $123127, %rax
        ret

This is because instruction and DAG combiners canonicalize

  (or (and x, C), D) -> (and (or, D), (C | D))

However, this is only profitable if (C & D) != 0. It gets in the way of the
3-addressification because the input bits are known to be zero.

llvm-svn: 97616

llvm-svn: 97615

disassembly only.

llvm-svn: 97614

llvm-svn: 97613

llvm-svn: 97612

llvm-svn: 97611

llvm-svn: 97610

llvm-svn: 97609

llvm-svn: 97608

come back to bite us at some point. 

llvm-svn: 97607

llvm-svn: 97606

declarations after the member has been explicitly specialized.  We already
did this after explicit instantiation definitions;  not doing it for
declarations meant that subsequent definitions would see a previous
member declaration with specialization kind "explicit instantiation decl",
which would then happily get overridden.

Fixes PR 6458.

llvm-svn: 97605

We still preprocess calls and fp return stuff.

llvm-svn: 97598

now that isel handles chains more aggressively.  This also
allows us to make isLegalToFold non-virtual.

llvm-svn: 97597

CopyToReg/CopyFromReg/INLINEASM.  These are annoying because
they have the same opcode before an after isel.  Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.

With that done, give IsLegalToFold a new flag that causes it to
ignore chains.  This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing.  This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.

I currently #if out the dead code in the X86 backend and MSP 
backend, I'll remove it for real in a follow-on patch.

The testcase changes are:
  test/CodeGen/X86/sse3.ll: we generate better code
  test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was 
      miscompiling this before, we now generate correct code
      Convert it to filecheck while I'm at it.
  test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
      folding to make anton happy. :)

llvm-svn: 97596

llvm-svn: 97595