a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.

llvm-svn: 74096

llvm-svn: 74087

Get rid of the global CFGOnly flag by threading a ShortNames parameters through the GraphViz rendering code.
Update other uses in the codebase for this change.

llvm-svn: 74084

llvm-svn: 74082

llvm-svn: 74065

Fixed a bug in LiveInterval scaling (failure to scale VNI defs correctly), removed old TODO comments.

llvm-svn: 74054

Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode).

llvm-svn: 74053

Only pad when the section size > 0 and move the code that deals
with globals initializers to a place we know for sure the global
is initialized.

llvm-svn: 73944

types for the target (I think).  This was breaking
the PPC32 calling sequence.

llvm-svn: 73900

Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced.

llvm-svn: 73898

llvm-svn: 73895

Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64.
Use a map to track global values to their symbol table indexes
Code cleanup and small fixes

llvm-svn: 73894

llvm-svn: 73816

llvm-svn: 73786

llvm-svn: 73784

taking so long to get to this!

llvm-svn: 73757

llvm-svn: 73750

llvm-svn: 73738

llvm-svn: 73736

llvm-svn: 73727

On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.

llvm-svn: 73720

- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.

llvm-svn: 73671

llvm-svn: 73634

llvm-svn: 73483

llvm-svn: 73480

llvm-svn: 73479

If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead.

TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.

llvm-svn: 73478

support for x86, and UMULO/SMULO for many architectures, including PPC 
(PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's
not bad.

llvm-svn: 73477

llvm-svn: 73464

llvm-svn: 73457

Owen Anderson 2009-06-15: Remember to clear out our maps to prevent crashing.

llvm-svn: 73438

unsupported inline asm construct, rather than verifying a code invariant.

llvm-svn: 73435

llvm-svn: 73426

llvm-svn: 73423

incomming chain of the RETURN node. The incomming chain must
be the outgoing chain of the CALL node. This causes the
backend to identify tail calls that are not tail calls. This
patch fixes this.

llvm-svn: 73387

- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381

llvm-svn: 73362

Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.

llvm-svn: 73346

Introduce new BinaryObject (blob) class, ELF Writer modified to use it. BinaryObject.h by Aaron Gray

llvm-svn: 73333

consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291