llvm-svn: 122444

loads properly.  We miscompiled the testcase into:

_test:                                  ## @test
	movl	$128, (%rdi)
	movzbl	1(%rdi), %eax
	ret

Now we get a proper:

_test:                                  ## @test
	movl	$128, (%rdi)
	movsbl	(%rdi), %eax
	movzbl	%ah, %eax
	ret

This fixes PR8757.

llvm-svn: 122392

unhanded cases faster and simplify code.

llvm-svn: 122391

llvm-svn: 122389

the same physical register. Simplifies the fix from the previous
checkin r122211.

llvm-svn: 122370

llvm-svn: 122368

the shift type was needed one place, the shift count
type another.  The transform in 123555 had the same
problem.

llvm-svn: 122366

llvm-svn: 122360

llvm-svn: 122355

count operand.  These should be the same but apparently are
not always, and this is cleaner anyway.  This improves the
code in an existing test.

llvm-svn: 122354

llvm-svn: 122353

llvm-svn: 122349

llvm-svn: 122345

llvm-svn: 122342

of the problems with my last attempt were in the updating of LiveIntervals
rather than the coalescing itself. Therefore, I decided to get that right first
by essentially reimplementing the existing PHIElimination using LiveIntervals.

It works correctly, with only a few tests failing (which may not be legitimate
failures) and no new verifier failures (at least as far as I can tell, I didn't
count the number per file).

llvm-svn: 122321

something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310

they are just as useless, but at least a bit more gramatical

llvm-svn: 122305

Edge bundles is an annotation on the CFG that turns it into a bipartite directed
graph where each basic block is connected to an outgoing and an ingoing bundle.
These bundles are useful for identifying regions of the CFG for live range
splitting.

llvm-svn: 122301

llvm-svn: 122296

llvm-svn: 122259

out-edges. Fixes PR8824.

llvm-svn: 122228

begin at DEF slots. Fixes the second half of PR8813.

llvm-svn: 122225

llvm-svn: 122224

ARM (and other 32-bit-only) targets support for i8 and i16 overflow 
multiplies.  The generated code isn't great, but this at least fixes
CodeGen/Generic/overflow.ll when running on ARM hosts.

llvm-svn: 122221

the register; it may be a dead def instead. Fixes PR8820.

llvm-svn: 122218

Imagine we see:

EFLAGS = inst1
EFLAGS = inst2 FLAGS
gpr = inst3 EFLAGS

Previously, we would refuse to schedule inst2 because it clobbers
the EFLAGS of the predecessor.  However, it also uses the EFLAGS
of the predecessor, so it is safe to emit.  SDep edges ensure that
the right order happens already anyway.

This fixes 2 testsuite crashes with the X86 patch I'm going to
commit next.

llvm-svn: 122211

llvm-svn: 122209

llvm-svn: 122208

PR8822.

llvm-svn: 122207

half of PR8813.

llvm-svn: 122205

ConnectedVNInfoEqClasses::Classify().

llvm-svn: 122202

llvm-svn: 122199

llvm-svn: 122197

llvm-svn: 122193

enough to teach it that ADDE(0,0) is known 0 except the 
low bit, for example.

llvm-svn: 122191

alternative register allocator that does not require LiveIntervals by specifying
it on the command-line for a target that has StrongPHIElimination enabled by
default.

These checks are pretty meaningless anyways, since StrongPHIElimination and
PHIElimination are never used at the same time.

llvm-svn: 122176

isel is *required* to split the edge.  PHI values get evaluated
on the edge, not in their predecessor block.

llvm-svn: 122170

llvm-svn: 122135

use before rematerializing the load.

This allows us to produce:

    addps	LCPI0_1(%rip), %xmm2

Instead of:

    movaps	LCPI0_1(%rip), %xmm3
    addps	%xmm3, %xmm2

Saving a register and an instruction. The standard spiller already knows how to
do this.

llvm-svn: 122133

llvm-svn: 122132